//
//===----------------------------------------------------------------------===//
//
-// This file contains the Cell implementation of the MRegisterInfo class.
+// This file contains the Cell implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
-#include <iostream>
using namespace llvm;
case SPU::R126: return 126;
case SPU::R127: return 127;
default:
- std::cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
+ cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
abort();
}
}
{
}
-void
-SPURegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIdx,
- const TargetRegisterClass *RC) const
-{
- MachineOpCode opc;
- if (RC == SPU::GPRCRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr128
- : SPU::STQXr128;
- } else if (RC == SPU::R64CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr64
- : SPU::STQXr64;
- } else if (RC == SPU::R64FPRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr64
- : SPU::STQXr64;
- } else if (RC == SPU::R32CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr32
- : SPU::STQXr32;
- } else if (RC == SPU::R32FPRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr32
- : SPU::STQXr32;
- } else if (RC == SPU::R16CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
- SPU::STQDr16
- : SPU::STQXr16;
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
-
- addFrameReference(BuildMI(MBB, MI, TII.get(opc))
- .addReg(SrcReg, false, false, isKill), FrameIdx);
-}
-
-void SPURegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- cerr << "storeRegToAddr() invoked!\n";
- abort();
-
- if (Addr[0].isFrameIndex()) {
- /* do what storeRegToStackSlot does here */
- } else {
- unsigned Opc = 0;
- if (RC == SPU::GPRCRegisterClass) {
- /* Opc = PPC::STW; */
- } else if (RC == SPU::R16CRegisterClass) {
- /* Opc = PPC::STD; */
- } else if (RC == SPU::R32CRegisterClass) {
- /* Opc = PPC::STFD; */
- } else if (RC == SPU::R32FPRegisterClass) {
- /* Opc = PPC::STFD; */
- } else if (RC == SPU::R64FPRegisterClass) {
- /* Opc = PPC::STFS; */
- } else if (RC == SPU::VECREGRegisterClass) {
- /* Opc = PPC::STVX; */
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
- .addReg(SrcReg, false, false, isKill);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- }
-}
-
-void
-SPURegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC) const
-{
- MachineOpCode opc;
- if (RC == SPU::GPRCRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr128
- : SPU::LQXr128;
- } else if (RC == SPU::R64CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr64
- : SPU::LQXr64;
- } else if (RC == SPU::R64FPRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr64
- : SPU::LQXr64;
- } else if (RC == SPU::R32CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr32
- : SPU::LQXr32;
- } else if (RC == SPU::R32FPRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr32
- : SPU::LQXr32;
- } else if (RC == SPU::R16CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr16
- : SPU::LQXr16;
- } else {
- assert(0 && "Unknown regclass in loadRegFromStackSlot!");
- abort();
- }
-
- addFrameReference(BuildMI(MBB, MI, TII.get(opc)).addReg(DestReg), FrameIdx);
-}
-
-/*!
- \note We are really pessimistic here about what kind of a load we're doing.
- */
-void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs)
- const {
- cerr << "loadRegToAddr() invoked!\n";
- abort();
-
- if (Addr[0].isFrameIndex()) {
- /* do what loadRegFromStackSlot does here... */
- } else {
- unsigned Opc = 0;
- if (RC == SPU::R8CRegisterClass) {
- /* do brilliance here */
- } else if (RC == SPU::R16CRegisterClass) {
- /* Opc = PPC::LWZ; */
- } else if (RC == SPU::R32CRegisterClass) {
- /* Opc = PPC::LD; */
- } else if (RC == SPU::R32FPRegisterClass) {
- /* Opc = PPC::LFD; */
- } else if (RC == SPU::R64FPRegisterClass) {
- /* Opc = PPC::LFS; */
- } else if (RC == SPU::VECREGRegisterClass) {
- /* Opc = PPC::LVX; */
- } else if (RC == SPU::GPRCRegisterClass) {
- /* Opc = something else! */
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- }
-}
-
-void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned DestReg,
- const MachineInstr *Orig) const {
- MachineInstr *MI = Orig->clone();
- MI->getOperand(0).setReg(DestReg);
- MBB.insert(I, MI);
-}
-
// SPU's 128-bit registers used for argument passing:
static const unsigned SPU_ArgRegs[] = {
SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
return SPU_ArgRegs;
}
-const unsigned
+unsigned
SPURegisterInfo::getNumArgRegs()
{
return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
*/
BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
- Reserved.set(SPU::R0); // LR
- Reserved.set(SPU::R1); // SP
- Reserved.set(SPU::R2); // environment pointer
+ Reserved.set(SPU::R0); // LR
+ Reserved.set(SPU::R1); // SP
+ Reserved.set(SPU::R2); // environment pointer
return Reserved;
}
-/// foldMemoryOperand - SPU, like PPC, can only fold spills into
-/// copy instructions, turning them into load/store instructions.
-MachineInstr *
-SPURegisterInfo::foldMemoryOperand(MachineInstr *MI,
- SmallVectorImpl<unsigned> &Ops,
- int FrameIndex) const
-{
-#if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
- if (Ops.size() != 1) return NULL;
-
- unsigned OpNum = Ops[0];
- unsigned Opc = MI->getOpcode();
- MachineInstr *NewMI = 0;
-
- if ((Opc == SPU::ORr32
- || Opc == SPU::ORv4i32)
- && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
- if (OpNum == 0) { // move -> store
- unsigned InReg = MI->getOperand(1).getReg();
- if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
- NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
- FrameIndex);
- }
- } else { // move -> load
- unsigned OutReg = MI->getOperand(0).getReg();
- Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
- NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
- }
- }
-
- if (NewMI)
- NewMI->copyKillDeadInfo(MI);
-
- return NewMI;
-#else
- return 0;
-#endif
-}
-
-/// General-purpose load/store fold to operand code
-MachineInstr *
-SPURegisterInfo::foldMemoryOperand(MachineInstr *MI,
- SmallVectorImpl<unsigned> &Ops,
- MachineInstr *LoadMI) const
-{
- return 0;
-}
-
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
void
SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
- RegScavenger *RS) const
+ RegScavenger *RS) const
{
unsigned i = 0;
MachineInstr &MI = *II;
if (hasDebugInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId).addImm(0);
}
// Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
if (isS10Constant(FrameSize)) {
// Spill $sp to adjusted $sp
BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
- .addReg(SPU::R1);
+ .addReg(SPU::R1);
// Adjust $sp by required amout
BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
- .addImm(FrameSize);
+ .addImm(FrameSize);
} else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
// $r2 to adjust $sp:
.addImm(-16)
.addReg(SPU::R1);
BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
- .addImm(FrameSize);
+ .addImm(FrameSize);
BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
.addReg(SPU::R2)
.addReg(SPU::R1);
// Add callee saved registers to move list.
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
- int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
- unsigned Reg = CSI[I].getReg();
- if (Reg == SPU::R0) continue;
- MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
- MachineLocation CSSrc(Reg);
- Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
+ int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
+ unsigned Reg = CSI[I].getReg();
+ if (Reg == SPU::R0) continue;
+ MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
+ MachineLocation CSSrc(Reg);
+ Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
}
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId).addImm(0);
MachineLocation FPDst(SPU::R1);
MachineLocation FPSrc(MachineLocation::VirtualFP);
MachineBasicBlock::iterator MBBI = prior(MBB.end());
// Insert terminator label
unsigned BranchLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId);
+ BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0);
}
}
}
.addReg(SPU::R1);
BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
.addReg(SPU::R1)
- .addImm(FrameSize);
+ .addImm(FrameSize);
} else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
// $r2 to adjust $sp:
.addImm(16)
.addReg(SPU::R1);
BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
- .addImm(FrameSize);
+ .addImm(FrameSize);
BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
.addReg(SPU::R1)
.addReg(SPU::R2);
projects / oota-llvm.git / blobdiff