[Hexagon] Allocate MCInst in the MCContext to avoid leaking it.

[oota-llvm.git] / lib / Target / Hexagon / AsmParser / HexagonAsmParser.cpp

diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index ee3d177d07d827562e689e0f2dc5c65b1f5be2e3..369bb46c44eb9f34f03a7b3dfc9897a35a17b269 100644 (file)
--- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -87,8 +87,6 @@ class HexagonAsmParser : public MCTargetAsmParser {
   MCAssembler *getAssembler() const { return Assembler; }
   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
 
-  unsigned ArchVersion;
-
   bool equalIsAsmAssignment() override { return false; }
   bool isLabel(AsmToken &Token) override;
 
@@ -114,7 +112,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
-                               uint64_t &ErrorInfo, bool MatchingInlineAsm);
+                               uint64_t &ErrorInfo, bool MatchingInlineAsm) override;
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
   void OutOfRange(SMLoc IDLoc, long long Val, long long Max);
@@ -162,13 +160,14 @@ public:
   bool parseExpressionOrOperand(OperandVector &Operands);
   bool parseExpression(MCExpr const *& Expr);
   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
-                                SMLoc NameLoc, OperandVector &Operands) {
+                                SMLoc NameLoc, OperandVector &Operands) override
+  {
     llvm_unreachable("Unimplemented");
   }
   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
-                                AsmToken ID, OperandVector &Operands);
+                                AsmToken ID, OperandVector &Operands) override;
 
-  virtual bool ParseDirective(AsmToken DirectiveID);
+  virtual bool ParseDirective(AsmToken DirectiveID) override;
 };
 
 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
@@ -872,7 +871,7 @@ bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                           MatchingInlineAsm, MustExtend))
     return true;
   HexagonMCInstrInfo::extendIfNeeded(
-      MCII, MCB, *SubInst,
+      getParser().getContext(), MCII, MCB, *SubInst,
       HexagonMCInstrInfo::isExtended(MCII, *SubInst) || MustExtend);
   MCB.addOperand(MCOperand::createInst(SubInst));
   if (!InBrackets)
@@ -1190,6 +1189,7 @@ bool HexagonAsmParser::isLabel(AsmToken &Token) {
     return true;
   if (!MatchRegisterName(String.lower()))
     return true;
+  (void)Second;
   assert(Second.is(AsmToken::Colon));
   StringRef Raw (String.data(), Third.getString().data() - String.data() +
                  Third.getString().size());
@@ -1566,6 +1566,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
     MCOperand &MO = Inst.getOperand(2);
     int64_t Value;
     bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
+    (void)Success;
     assert(Success && "Assured by matcher");
     if (Value == 0) {
       MCInst TmpInst;