//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "hwloops"
#include "llvm/ADT/SmallSet.h"
#include "Hexagon.h"
#include "HexagonTargetMachine.h"
using namespace llvm;
+#define DEBUG_TYPE "hwloops"
+
#ifndef NDEBUG
static cl::opt<int> HWLoopLimit("max-hwloop", cl::Hidden, cl::init(-1));
#endif
initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry());
}
- virtual bool runOnMachineFunction(MachineFunction &MF);
+ bool runOnMachineFunction(MachineFunction &MF) override;
- const char *getPassName() const { return "Hexagon Hardware Loops"; }
+ const char *getPassName() const override { return "Hexagon Hardware Loops"; }
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>();
AU.addRequired<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
return Contents.ImmVal;
}
- void print(raw_ostream &OS, const TargetMachine *TM = 0) const {
- const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
+ void print(raw_ostream &OS, const TargetMachine *TM = nullptr) const {
+ const TargetRegisterInfo *TRI =
+ TM ? TM->getSubtargetImpl()->getRegisterInfo() : nullptr;
if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
if (isImm()) { OS << Contents.ImmVal; }
}
MRI = &MF.getRegInfo();
MDT = &getAnalysis<MachineDominatorTree>();
TM = static_cast<const HexagonTargetMachine*>(&MF.getTarget());
- TII = static_cast<const HexagonInstrInfo*>(TM->getInstrInfo());
- TRI = static_cast<const HexagonRegisterInfo*>(TM->getRegisterInfo());
+ TII = static_cast<const HexagonInstrInfo *>(
+ TM->getSubtargetImpl()->getInstrInfo());
+ TRI = static_cast<const HexagonRegisterInfo *>(
+ TM->getSubtargetImpl()->getRegisterInfo());
for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end();
I != E; ++I) {
} // for (instr)
SmallVector<MachineOperand,2> Cond;
- MachineBasicBlock *TB = 0, *FB = 0;
+ MachineBasicBlock *TB = nullptr, *FB = nullptr;
bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
if (NotAnalyzed)
return false;
"Loop must have more than one incoming edge!");
MachineBasicBlock *Backedge = *PI++;
if (PI == TopMBB->pred_end()) // dead loop?
- return 0;
+ return nullptr;
MachineBasicBlock *Incoming = *PI++;
if (PI != TopMBB->pred_end()) // multiple backedges?
- return 0;
+ return nullptr;
// Make sure there is one incoming and one backedge and determine which
// is which.
if (L->contains(Incoming)) {
if (L->contains(Backedge))
- return 0;
+ return nullptr;
std::swap(Incoming, Backedge);
} else if (!L->contains(Backedge))
- return 0;
+ return nullptr;
// Look for the cmp instruction to determine if we can get a useful trip
// count. The trip count can be either a register or an immediate. The
// location of the value depends upon the type (reg or imm).
MachineBasicBlock *Latch = L->getLoopLatch();
if (!Latch)
- return 0;
+ return nullptr;
unsigned IVReg = 0;
int64_t IVBump = 0;
MachineInstr *IVOp;
bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);
if (!FoundIV)
- return 0;
+ return nullptr;
MachineBasicBlock *Preheader = L->getLoopPreheader();
- MachineOperand *InitialValue = 0;
+ MachineOperand *InitialValue = nullptr;
MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) {
MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB();
IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
}
if (!InitialValue)
- return 0;
+ return nullptr;
SmallVector<MachineOperand,2> Cond;
- MachineBasicBlock *TB = 0, *FB = 0;
+ MachineBasicBlock *TB = nullptr, *FB = nullptr;
bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
if (NotAnalyzed)
- return 0;
+ return nullptr;
MachineBasicBlock *Header = L->getHeader();
// TB must be non-null. If FB is also non-null, one of them must be
assert (TB && "Latch block without a branch?");
assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");
if (!TB || (FB && TB != Header && FB != Header))
- return 0;
+ return nullptr;
// Branches of form "if (!P) ..." cause HexagonInstrInfo::AnalyzeBranch
// to put imm(0), followed by P in the vector Cond.
bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2,
Mask, ImmValue);
if (!AnalyzedCmp)
- return 0;
+ return nullptr;
// The comparison operator type determines how we compute the loop
// trip count.
bool isSwapped = false;
const MachineOperand &Op1 = CondI->getOperand(1);
const MachineOperand &Op2 = CondI->getOperand(2);
- const MachineOperand *EndValue = 0;
+ const MachineOperand *EndValue = nullptr;
if (Op1.isReg()) {
if (Op2.isImm() || Op1.getReg() == IVReg)
}
if (!EndValue)
- return 0;
+ return nullptr;
switch (CondOpc) {
case Hexagon::CMPEQri:
case Hexagon::CMPbEQri_V4:
case Hexagon::CMPhEQri_V4: {
if (IVBump != 1)
- return 0;
+ return nullptr;
int64_t InitV, EndV;
// Since the comparisons are "ri", the EndValue should be an
// Allow InitialValue to be a register defined with an immediate.
if (InitialValue->isReg()) {
if (!defWithImmediate(InitialValue->getReg()))
- return 0;
+ return nullptr;
InitV = getImmediate(*InitialValue);
} else {
assert(InitialValue->isImm());
InitV = InitialValue->getImm();
}
if (InitV >= EndV)
- return 0;
+ return nullptr;
if (CondOpc == Hexagon::CMPbEQri_V4) {
if (!isInt<8>(InitV) || !isInt<8>(EndV))
- return 0;
+ return nullptr;
} else { // Hexagon::CMPhEQri_V4
if (!isInt<16>(InitV) || !isInt<16>(EndV))
- return 0;
+ return nullptr;
}
Cmp = !Negated ? Comparison::EQ : Comparison::NE;
break;
}
default:
- return 0;
+ return nullptr;
}
if (isSwapped)
unsigned R = InitialValue->getReg();
MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
if (!MDT->properlyDominates(DefBB, Header))
- return 0;
+ return nullptr;
OldInsts.push_back(MRI->getVRegDef(R));
}
if (EndValue->isReg()) {
unsigned R = EndValue->getReg();
MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
if (!MDT->properlyDominates(DefBB, Header))
- return 0;
+ return nullptr;
}
return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
Comparison::Kind Cmp) const {
// Cannot handle comparison EQ, i.e. while (A == B).
if (Cmp == Comparison::EQ)
- return 0;
+ return nullptr;
// Check if either the start or end values are an assignment of an immediate.
// If so, use the immediate value rather than the register.
// If loop executes while iv is "less" with the iv value going down, then
// the iv must wrap.
if (CmpLess && IVBump < 0)
- return 0;
+ return nullptr;
// If loop executes while iv is "greater" with the iv value going up, then
// the iv must wrap.
if (CmpGreater && IVBump > 0)
- return 0;
+ return nullptr;
if (Start->isImm() && End->isImm()) {
// Both, start and end are immediates.
int64_t EndV = End->getImm();
int64_t Dist = EndV - StartV;
if (Dist == 0)
- return 0;
+ return nullptr;
bool Exact = (Dist % IVBump) == 0;
if (Cmp == Comparison::NE) {
if (!Exact)
- return 0;
+ return nullptr;
if ((Dist < 0) ^ (IVBump < 0))
- return 0;
+ return nullptr;
}
// For comparisons that include the final value (i.e. include equality
uint64_t Count = Dist1;
if (Count > 0xFFFFFFFFULL)
- return 0;
+ return nullptr;
return new CountValue(CountValue::CV_Immediate, Count);
}
// If the induction variable bump is not a power of 2, quit.
// Othwerise we'd need a general integer division.
if (!isPowerOf2_64(abs64(IVBump)))
- return 0;
+ return nullptr;
MachineBasicBlock *PH = Loop->getLoopPreheader();
assert (PH && "Should have a preheader by now");
// Hardware loops cannot handle 64-bit registers. If it's a double
// register, it has to have a subregister.
if (!SR && RC == &Hexagon::DoubleRegsRegClass)
- return 0;
+ return nullptr;
const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
// Compute DistR (register with the distance between Start and End).
// this instruction is dead: both it (and the phi node) can be removed.
use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);
use_nodbg_iterator End = MRI->use_nodbg_end();
- if (llvm::next(I) != End || !I.getOperand().getParent()->isPHI())
+ if (std::next(I) != End || !I->getParent()->isPHI())
return false;
- MachineInstr *OnePhi = I.getOperand().getParent();
+ MachineInstr *OnePhi = I->getParent();
for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
const MachineOperand &OPO = OnePhi->getOperand(j);
if (!OPO.isReg() || !OPO.isDef())
use_nodbg_iterator nextJ;
for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg);
J != End; J = nextJ) {
- nextJ = llvm::next(J);
- MachineOperand &Use = J.getOperand();
+ nextJ = std::next(J);
+ MachineOperand &Use = *J;
MachineInstr *UseMI = Use.getParent();
// If the phi node has a user that is not MI, bail...
MachineRegisterInfo::use_iterator nextI;
for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
E = MRI->use_end(); I != E; I = nextI) {
- nextI = llvm::next(I); // I is invalidated by the setReg
- MachineOperand &Use = I.getOperand();
- MachineInstr *UseMI = Use.getParent();
+ nextI = std::next(I); // I is invalidated by the setReg
+ MachineOperand &Use = *I;
+ MachineInstr *UseMI = I->getParent();
if (UseMI == MI)
continue;
if (Use.isDebug())
MachineBasicBlock *LastMBB = L->getExitingBlock();
// Don't generate hw loop if the loop has more than one exit.
- if (LastMBB == 0)
+ if (!LastMBB)
return false;
MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
SmallVector<MachineInstr*, 2> OldInsts;
// Are we able to determine the trip count for the loop?
CountValue *TripCount = getLoopTripCount(L, OldInsts);
- if (TripCount == 0)
+ if (!TripCount)
return false;
// Is the trip count available in the preheader?
if (LastI != LastMBB->end())
LastI = LastMBB->erase(LastI);
SmallVector<MachineOperand, 0> Cond;
- TII->InsertBranch(*LastMBB, BranchTarget, 0, Cond, LastIDL);
+ TII->InsertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL);
}
} else {
// Conditional branch to loop start; just delete it.
// Out of order.
unsigned PredR = CmpI->getOperand(0).getReg();
bool FoundBump = false;
- instr_iterator CmpIt = CmpI, NextIt = llvm::next(CmpIt);
+ instr_iterator CmpIt = CmpI, NextIt = std::next(CmpIt);
for (instr_iterator I = NextIt, E = BB->instr_end(); I != E; ++I) {
MachineInstr *In = &*I;
for (unsigned i = 0, n = In->getNumOperands(); i < n; ++i) {
if (In == BumpI) {
instr_iterator After = BumpI;
instr_iterator From = CmpI;
- BB->splice(llvm::next(After), BB, From);
+ BB->splice(std::next(After), BB, From);
FoundBump = true;
break;
}
case Hexagon::CONST64_Int_Real:
return DI;
}
- return 0;
+ return nullptr;
}
if (IndRegs.empty())
return false;
- MachineBasicBlock *TB = 0, *FB = 0;
+ MachineBasicBlock *TB = nullptr, *FB = nullptr;
SmallVector<MachineOperand,2> Cond;
// AnalyzeBranch returns true if it fails to analyze branch.
bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false);
return false;
SmallSet<unsigned,2> CmpRegs;
- MachineOperand *CmpImmOp = 0;
+ MachineOperand *CmpImmOp = nullptr;
// Go over all operands to the compare and look for immediate and register
// operands. Assume that if the compare has a single register use and a
DebugLoc DL;
if (!Latch || Header->hasAddressTaken())
- return 0;
+ return nullptr;
typedef MachineBasicBlock::instr_iterator instr_iterator;
typedef std::vector<MachineBasicBlock*> MBBVector;
MBBVector Preds(Header->pred_begin(), Header->pred_end());
SmallVector<MachineOperand,2> Tmp1;
- MachineBasicBlock *TB = 0, *FB = 0;
+ MachineBasicBlock *TB = nullptr, *FB = nullptr;
if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false))
- return 0;
+ return nullptr;
for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
MachineBasicBlock *PB = *I;
if (PB != Latch) {
bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false);
if (NotAnalyzed)
- return 0;
+ return nullptr;
}
}
SmallVector<MachineOperand,1> Tmp2;
SmallVector<MachineOperand,1> EmptyCond;
- TB = FB = 0;
+ TB = FB = nullptr;
for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
MachineBasicBlock *PB = *I;
(void)NotAnalyzed; // suppress compiler warning
assert (!NotAnalyzed && "Should be analyzable!");
if (TB != Header && (Tmp2.empty() || FB != Header))
- TII->InsertBranch(*PB, NewPH, 0, EmptyCond, DL);
+ TII->InsertBranch(*PB, NewPH, nullptr, EmptyCond, DL);
PB->ReplaceUsesOfBlockWith(Header, NewPH);
}
}
// It can happen that the latch block will fall through into the header.
// Insert an unconditional branch to the header.
- TB = FB = 0;
+ TB = FB = nullptr;
bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false);
(void)LatchNotAnalyzed; // suppress compiler warning
assert (!LatchNotAnalyzed && "Should be analyzable!");
if (!TB && !FB)
- TII->InsertBranch(*Latch, Header, 0, EmptyCond, DL);
+ TII->InsertBranch(*Latch, Header, nullptr, EmptyCond, DL);
// Finally, the branch from the preheader to the header.
- TII->InsertBranch(*NewPH, Header, 0, EmptyCond, DL);
+ TII->InsertBranch(*NewPH, Header, nullptr, EmptyCond, DL);
NewPH->addSuccessor(Header);
return NewPH;
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