llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC.

[oota-llvm.git] / lib / Target / Hexagon / HexagonISelLowering.cpp

diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index 8d2d3fd8f6a79f4a73f7a25ddb3f95980b16f132..88965a5775f3f7225f66970703666e92a47989dd 100644 (file)
--- a/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -28,18 +28,19 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "HexagonMachineFunctionInfo.h"
-#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/raw_ostream.h"
 
-const unsigned Hexagon_MAX_RET_SIZE = 64;
 using namespace llvm;
 
+const unsigned Hexagon_MAX_RET_SIZE = 64;
+
 static cl::opt<bool>
 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
                cl::desc("Control jump table emission on Hexagon target"));
@@ -113,8 +114,6 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
     return false;
   }
   llvm_unreachable(0);
-
-  return true;
 }
 
 
@@ -161,7 +160,7 @@ static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
 
-  static const unsigned RegList[] = {
+  static const uint16_t RegList[] = {
     Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
     Hexagon::R5
   };
@@ -184,10 +183,10 @@ static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
     return false;
   }
 
-  static const unsigned RegList1[] = {
+  static const uint16_t RegList1[] = {
     Hexagon::D1, Hexagon::D2
   };
-  static const unsigned RegList2[] = {
+  static const uint16_t RegList2[] = {
     Hexagon::R1, Hexagon::R3
   };
   if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
@@ -305,9 +304,6 @@ HexagonTargetLowering::LowerReturn(SDValue Chain,
   // Analyze return values of ISD::RET
   CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
 
-  SDValue StackPtr = DAG.getRegister(TM.getRegisterInfo()->getStackRegister(),
-                                     MVT::i32);
-
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
@@ -320,8 +316,6 @@ HexagonTargetLowering::LowerReturn(SDValue Chain,
   // Copy the result values into the output registers.
   for (unsigned i = 0; i != RVLocs.size(); ++i) {
     CCValAssign &VA = RVLocs[i];
-    SDValue Ret = OutVals[i];
-    ISD::ArgFlagsTy Flags = Outs[i].Flags;
 
     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
 
@@ -378,7 +372,7 @@ HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
 SDValue
 HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
                                  CallingConv::ID CallConv, bool isVarArg,
-                                 bool &isTailCall,
+                                 bool doesNotRet, bool &isTailCall,
                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
                                  const SmallVectorImpl<SDValue> &OutVals,
                                  const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -456,7 +450,7 @@ HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
     switch (VA.getLocInfo()) {
       default:
         // Loc info must be one of Full, SExt, ZExt, or AExt.
-        assert(0 && "Unknown loc info!");
+        llvm_unreachable("Unknown loc info!");
       case CCValAssign::Full:
         break;
       case CCValAssign::SExt:
@@ -650,7 +644,7 @@ bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
     return false;
   }
 
-  bool isInc;
+  bool isInc = false;
   bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
                                         isInc, DAG);
   // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
@@ -847,12 +841,12 @@ const {
       EVT RegVT = VA.getLocVT();
       if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) {
         unsigned VReg =
-          RegInfo.createVirtualRegister(Hexagon::IntRegsRegisterClass);
+          RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
       } else if (RegVT == MVT::i64) {
         unsigned VReg =
-          RegInfo.createVirtualRegister(Hexagon::DoubleRegsRegisterClass);
+          RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
       } else {
@@ -1017,10 +1011,10 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
     TM(targetmachine) {
 
     // Set up the register classes.
-    addRegisterClass(MVT::i32, Hexagon::IntRegsRegisterClass);
-    addRegisterClass(MVT::i64, Hexagon::DoubleRegsRegisterClass);
+    addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
+    addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
 
-    addRegisterClass(MVT::i1, Hexagon::PredRegsRegisterClass);
+    addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
 
     computeRegisterProperties();
 
@@ -1250,7 +1244,9 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
     setOperationAction(ISD::FREM , MVT::f32, Expand);
     setOperationAction(ISD::CTPOP, MVT::i32, Expand);
     setOperationAction(ISD::CTTZ , MVT::i32, Expand);
+    setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
     setOperationAction(ISD::CTLZ , MVT::i32, Expand);
+    setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
     setOperationAction(ISD::ROTL , MVT::i32, Expand);
     setOperationAction(ISD::ROTR , MVT::i32, Expand);
     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
@@ -1303,6 +1299,7 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
     // Needed for DYNAMIC_STACKALLOC expansion.
     unsigned StackRegister = TM.getRegisterInfo()->getStackRegister();
     setStackPointerRegisterToSaveRestore(StackRegister);
+    setSchedulingPreference(Sched::VLIW);
 }
 
 
@@ -1349,12 +1346,12 @@ bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
 SDValue
 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
-    default: assert(0 && "Should not custom lower this!");
+    default: llvm_unreachable("Should not custom lower this!");
       // Frame & Return address.  Currently unimplemented.
     case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
     case ISD::FRAMEADDR:  return LowerFRAMEADDR(Op, DAG);
     case ISD::GlobalTLSAddress:
-                          assert(0 && "TLS not implemented for Hexagon.");
+                          llvm_unreachable("TLS not implemented for Hexagon.");
     case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
     case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
     case ISD::GlobalAddress:      return LowerGLOBALADDRESS(Op, DAG);
@@ -1386,10 +1383,8 @@ const {
       FuncInfo->addAllocaAdjustInst(MI);
       return BB;
     }
-    default:
-      assert(false && "Unexpected instr type to insert");
+    default: llvm_unreachable("Unexpected instr type to insert");
   } // switch
-  return NULL;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1405,16 +1400,16 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const
     case 'r':   // R0-R31
        switch (VT.getSimpleVT().SimpleTy) {
        default:
-         assert(0 && "getRegForInlineAsmConstraint Unhandled data type");
+         llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
        case MVT::i32:
        case MVT::i16:
        case MVT::i8:
-         return std::make_pair(0U, Hexagon::IntRegsRegisterClass);
+         return std::make_pair(0U, &Hexagon::IntRegsRegClass);
        case MVT::i64:
-         return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
+         return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
       }
     default:
-      assert(0 && "Unknown asm register class");
+      llvm_unreachable("Unknown asm register class");
     }
   }