}
}
-//===----------------------------------------------------------------------===//
-// Instructions
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// http://qualnet.qualcomm.com/~erich/v1/htmldocs/index.html
-// http://qualnet.qualcomm.com/~erich/v2/htmldocs/index.html
-// http://qualnet.qualcomm.com/~erich/v3/htmldocs/index.html
-// http://qualnet.qualcomm.com/~erich/v4/htmldocs/index.html
-// http://qualnet.qualcomm.com/~erich/v5/htmldocs/index.html
-//===----------------------------------------------------------------------===//
-
//===----------------------------------------------------------------------===//
// ALU32/ALU +
//===----------------------------------------------------------------------===//
"$dst = $src1",
[]>;
-
// Transfer control register.
let neverHasSideEffects = 1 in
def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
// Conditional add.
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
+ (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
"if ($src1) $dst = add($src2, #$src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
+ (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
"if (!$src1) $dst = add($src2, #$src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
+ (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
"if ($src1.new) $dst = add($src2, #$src3)",
[]>;
let neverHasSideEffects = 1, isPredicated = 1 in
def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3),
+ (ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
"if (!$src1.new) $dst = add($src2, #$src3)",
[]>;
"if (!$src1) $dst = $src2",
[]>;
-
let neverHasSideEffects = 1, isPredicated = 1 in
def TFR64_cPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
DoubleRegs:$src2),
// ALU32/PRED -
//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// ALU32/VH +
-//===----------------------------------------------------------------------===//
-// Vector add halfwords
-
-// Vector averagehalfwords
-
-// Vector subtract halfwords
-//===----------------------------------------------------------------------===//
-// ALU32/VH -
-//===----------------------------------------------------------------------===//
-
//===----------------------------------------------------------------------===//
// ALU64/ALU +
(i32 IntRegs:$src1))),
(i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
+def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
+ "$dst = maxu($src2, $src1)",
+ [(set (i32 IntRegs:$dst),
+ (i32 (select (i1 (setult (i32 IntRegs:$src2),
+ (i32 IntRegs:$src1))),
+ (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
+
+def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
+ DoubleRegs:$src2),
+ "$dst = max($src2, $src1)",
+ [(set (i64 DoubleRegs:$dst),
+ (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
+ (i64 DoubleRegs:$src1))),
+ (i64 DoubleRegs:$src1),
+ (i64 DoubleRegs:$src2))))]>;
+
+def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
+ DoubleRegs:$src2),
+ "$dst = maxu($src2, $src1)",
+ [(set (i64 DoubleRegs:$dst),
+ (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
+ (i64 DoubleRegs:$src1))),
+ (i64 DoubleRegs:$src1),
+ (i64 DoubleRegs:$src2))))]>;
+
// Minimum.
def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
"$dst = min($src2, $src1)",
(i32 IntRegs:$src1))),
(i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
+def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
+ "$dst = minu($src2, $src1)",
+ [(set (i32 IntRegs:$dst),
+ (i32 (select (i1 (setugt (i32 IntRegs:$src2),
+ (i32 IntRegs:$src1))),
+ (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
+
+def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
+ DoubleRegs:$src2),
+ "$dst = min($src2, $src1)",
+ [(set (i64 DoubleRegs:$dst),
+ (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
+ (i64 DoubleRegs:$src1))),
+ (i64 DoubleRegs:$src1),
+ (i64 DoubleRegs:$src2))))]>;
+
+def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
+ DoubleRegs:$src2),
+ "$dst = minu($src2, $src1)",
+ [(set (i64 DoubleRegs:$dst),
+ (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
+ (i64 DoubleRegs:$src1))),
+ (i64 DoubleRegs:$src1),
+ (i64 DoubleRegs:$src2))))]>;
+
// Subtract.
def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
DoubleRegs:$src2),
// ALU64/PERM -
//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// ALU64/VB +
-//===----------------------------------------------------------------------===//
-//
-//===----------------------------------------------------------------------===//
-// ALU64/VB -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ALU64/VH +
-//===----------------------------------------------------------------------===//
-//
-//===----------------------------------------------------------------------===//
-// ALU64/VH -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ALU64/VW +
-//===----------------------------------------------------------------------===//
-//
-//===----------------------------------------------------------------------===//
-// ALU64/VW -
-//===----------------------------------------------------------------------===//
-
//===----------------------------------------------------------------------===//
// CR +
//===----------------------------------------------------------------------===//
[]>;
-let neverHasSideEffects = 1, isPredicated = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_cNotPt : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, MEMri:$addr),
"if (!$src1) $dst = memd($addr)",
[]>;
-let neverHasSideEffects = 1, isPredicated = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_indexed_cPt : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
"if ($src1) $dst = memd($src2+#$src3)",
[]>;
-let neverHasSideEffects = 1, isPredicated = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_indexed_cNotPt : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
"if (!$src1) $dst = memd($src2+#$src3)",
[]>;
-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
+let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
def POST_LDrid_cPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
(ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
"if ($src1) $dst1 = memd($src2++#$src3)",
[],
"$src2 = $dst2">;
-let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
+let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in
def POST_LDrid_cNotPt : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2),
(ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3),
"if (!$src1) $dst1 = memd($src2++#$src3)",
[],
"$src2 = $dst2">;
-let neverHasSideEffects = 1, isPredicated = 1, isPredicated = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_cdnPt : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, MEMri:$addr),
"if ($src1.new) $dst = memd($addr)",
[]>;
-let neverHasSideEffects = 1, isPredicated = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, MEMri:$addr),
"if (!$src1.new) $dst = memd($addr)",
[]>;
-let neverHasSideEffects = 1, isPredicated = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_indexed_cdnPt : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
"if ($src1.new) $dst = memd($src2+#$src3)",
[]>;
-let neverHasSideEffects = 1, isPredicated = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def LDrid_indexed_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
"if (!$src1.new) $dst = memd($src2+#$src3)",
"$dst = memb($addr)",
[(set (i32 IntRegs:$dst), (i32 (sextloadi8 ADDRriS11_0:$addr)))]>;
-// Load byte any-extend
+// Load byte any-extend.
def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
(i32 (LDrib ADDRriS11_0:$addr)) >;
"$dst = memh($src1+#$offset)",
[(set (i32 IntRegs:$dst),
(i32 (sextloadi16 (add (i32 IntRegs:$src1),
- s11_1ImmPred:$offset))))] >;
+ s11_1ImmPred:$offset))))]>;
def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
(i32 (LDrih ADDRriS11_1:$addr))>;
// Load predicate.
let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
-def LDriw_pred : LDInst2<(outs PredRegs:$dst),
+def LDriw_pred : LDInst<(outs PredRegs:$dst),
(ins MEMri:$addr),
"Error; should not emit",
[]>;
[]>,
Requires<[NoV4T]>;
-let mayStore = 1, neverHasSideEffects = 1 in
-def STd_GP : STInst<(outs),
+let neverHasSideEffects = 1 in
+def STd_GP : STInst2<(outs),
(ins globaladdress:$global, DoubleRegs:$src),
"memd(#$global) = $src",
[]>,
// Store doubleword conditionally.
// if ([!]Pv) memd(Rs+#u6:3)=Rtt
// if (Pv) memd(Rs+#u6:3)=Rtt
-let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
+let AddedComplexity = 10, neverHasSideEffects = 1,
+ isPredicated = 1 in
def STrid_cPt : STInst2<(outs),
(ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
"if ($src1) memd($addr) = $src2",
[]>;
// if (!Pv) memd(Rs+#u6:3)=Rtt
-let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
+let AddedComplexity = 10, neverHasSideEffects = 1,
+ isPredicated = 1 in
def STrid_cNotPt : STInst2<(outs),
(ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
"if (!$src1) memd($addr) = $src2",
[]>;
// if (Pv) memd(Rs+#u6:3)=Rtt
-let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
+let AddedComplexity = 10, neverHasSideEffects = 1,
+ isPredicated = 1 in
def STrid_indexed_cPt : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
DoubleRegs:$src4),
[]>;
// if (!Pv) memd(Rs+#u6:3)=Rtt
-let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
+let AddedComplexity = 10, neverHasSideEffects = 1,
+ isPredicated = 1 in
def STrid_indexed_cNotPt : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
DoubleRegs:$src4),
// if ([!]Pv) memd(Rx++#s4:3)=Rtt
// if (Pv) memd(Rx++#s4:3)=Rtt
-let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1 in
+let AddedComplexity = 10, neverHasSideEffects = 1,
+ isPredicated = 1 in
def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
s4_3Imm:$offset),
[]>,
Requires<[NoV4T]>;
+// memb(#global)=Rt
let neverHasSideEffects = 1 in
-def STb_GP : STInst2<(outs),
+def STb_GP : STInst2<(outs),
(ins globaladdress:$global, IntRegs:$src),
"memb(#$global) = $src",
[]>,
[]>,
Requires<[NoV4T]>;
-let mayStore = 1, neverHasSideEffects = 1 in
-def STw_GP : STInst<(outs),
+let neverHasSideEffects = 1 in
+def STw_GP : STInst2<(outs),
(ins globaladdress:$global, IntRegs:$src),
"memw(#$global) = $src",
[]>,
// Store word conditionally.
// if ([!]Pv) memw(Rs+#u6:2)=Rt
// if (Pv) memw(Rs+#u6:2)=Rt
-let neverHasSideEffects = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def STriw_cPt : STInst2<(outs),
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
"if ($src1) memw($addr) = $src2",
[]>;
// if (!Pv) memw(Rs+#u6:2)=Rt
-let neverHasSideEffects = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def STriw_cNotPt : STInst2<(outs),
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
"if (!$src1) memw($addr) = $src2",
[]>;
// if (Pv) memw(Rs+#u6:2)=Rt
-let neverHasSideEffects = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def STriw_indexed_cPt : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
"if ($src1) memw($src2+#$src3) = $src4",
[]>;
// if (!Pv) memw(Rs+#u6:2)=Rt
-let neverHasSideEffects = 1 in
+let neverHasSideEffects = 1, isPredicated = 1 in
def STriw_indexed_cNotPt : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
"if (!$src1) memw($src2+#$src3) = $src4",
def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
(TOGBIT_31 (i32 IntRegs:$src1), 31)>;
-//===----------------------------------------------------------------------===//
-// STYPE/BIT -
-//===----------------------------------------------------------------------===//
-
-
-//===----------------------------------------------------------------------===//
-// STYPE/COMPLEX +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// STYPE/COMPLEX -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/PERM +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// STYPE/PERM -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/PRED +
-//===----------------------------------------------------------------------===//
-// STYPE/BIT -
-//===----------------------------------------------------------------------===//
-
-
-//===----------------------------------------------------------------------===//
-// STYPE/COMPLEX +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// STYPE/COMPLEX -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/PERM +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// STYPE/PERM -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/PRED +
-//===----------------------------------------------------------------------===//
// Predicate transfer.
let neverHasSideEffects = 1 in
def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
[(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
u6ImmPred:$src2))]>;
-def LSRd_ri_acc : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
- DoubleRegs:$src2,
- u6Imm:$src3),
- "$dst += lsr($src2, #$src3)",
- [(set DoubleRegs:$dst, (add DoubleRegs:$src1,
- (srl DoubleRegs:$src2,
- u6ImmPred:$src3)))],
- "$src1 = $dst">;
-
-// Shift by immediate and accumulate.
-def ASR_rr_acc : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$src1,
- IntRegs:$src2,
- IntRegs:$src3),
- "$dst += asr($src2, $src3)",
- [], "$src1 = $dst">;
-
// Shift by immediate and add.
let AddedComplexity = 100 in
def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
}
let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
- Defs = [PC, LC0], Uses = [SA0, LC0] in {
+ Defs = [PC, LC0], Uses = [SA0, LC0] in {
def ENDLOOP0 : Marker<(outs), (ins brtarget:$offset),
":endloop0",
[]>;
}
// Support for generating global address.
+// Taken from X86InstrInfo.td.
def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
SDTCisVT<0, i32>,
SDTCisVT<1, i32>,
def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
// HI/LO Instructions
-let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
-def LO : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
+let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
+def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst.l = #LO($global)",
[]>;
-let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
-def HI : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
+let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
+def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst.h = #HI($global)",
[]>;
-let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
-def LOi : LDInst<(outs IntRegs:$dst), (ins i32imm:$imm_value),
+let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
+def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
"$dst.l = #LO($imm_value)",
[]>;
-let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
-def HIi : LDInst<(outs IntRegs:$dst), (ins i32imm:$imm_value),
+let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
+def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
"$dst.h = #HI($imm_value)",
[]>;
-let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
-def LO_jt : LDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
+let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
+def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
"$dst.l = #LO($jt)",
[]>;
-let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
-def HI_jt : LDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
+let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
+def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
"$dst.h = #HI($jt)",
[]>;
-let isReMaterializable = 1, mayLoad = 1, neverHasSideEffects = 1 in
-def LO_label : LDInst<(outs IntRegs:$dst), (ins bblabel:$label),
+let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
+def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
"$dst.l = #LO($label)",
[]>;
-let isReMaterializable = 1, mayLoad = 1 , neverHasSideEffects = 1 in
-def HI_label : LDInst<(outs IntRegs:$dst), (ins bblabel:$label),
+let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
+def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
"$dst.h = #HI($label)",
[]>;
def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
u16ImmPred:$offset),
(i32 IntRegs:$src1)),
- (STriw_GP tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,
+ (STriw_GP tglobaladdr:$global, u16ImmPred:$offset,
+ (i32 IntRegs:$src1))>,
Requires<[NoV4T]>;
def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
(i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
subreg_loreg))))))>;
-// We want to prevent emiting pnot's as much as possible.
+// We want to prevent emitting pnot's as much as possible.
// Map brcond with an unsupported setcc to a JMP_cNot.
def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
bb:$offset),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
subreg_loreg)))), 32)),
subreg_loreg)))),
- (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
- (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
+ (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
+ (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
32)), subreg_loreg)))),
def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
-
def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
"$dst = $src1",
[(set (i32 IntRegs:$dst),
[(HexagonBR_JT (i32 IntRegs:$src))]>;
def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
-def HexagonWrapperCP: SDNode<"HexagonISD::WrapperCP", SDTIntUnaryOp>;
def : Pat<(HexagonWrapperJT tjumptable:$dst),
(i32 (CONST32_set_jt tjumptable:$dst))>;
-def : Pat<(HexagonWrapperCP tconstpool :$dst),
- (i32 (CONST32_set_jt tconstpool:$dst))>;
// XTYPE/SHIFT
(ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
!strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
[(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
- (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
+ (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
"$src1 = $dst">;
}
//===----------------------------------------------------------------------===//
// V5 Instructions -
//===----------------------------------------------------------------------===//
+
+