let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
- bit isNegCond, bit isTaken>
+ bit isNegCond, bit isTak>
: NVInst_V4<(outs),
(ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
"if ("#!if(isNegCond, "!","")#mnemonic#
"($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
"$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
- #!if(isTaken, "t","nt")#" $offset",
+ #!if(isTak, "t","nt")#" $offset",
[]>, Requires<[HasV4T]> {
bits<5> src1;
bits<5> RegOp; // Non-New-Value Operand
bits<11> offset;
+ let isTaken = isTak;
let isBrTaken = !if(isTaken, "true", "false");
let isPredicatedFalse = isNegCond;
let Inst{25-23} = majOp;
let Inst{22} = isNegCond;
let Inst{18-16} = Ns;
- let Inst{13} = isTaken;
+ let Inst{13} = isTak;
let Inst{12-8} = RegOp;
let Inst{21-20} = offset{10-9};
let Inst{7-1} = offset{8-2};
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
- bit isTaken>
+ bit isTak>
: NVInst_V4<(outs),
(ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
"if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
- #!if(isTaken, "t","nt")#" $offset",
+ #!if(isTak, "t","nt")#" $offset",
[]>, Requires<[HasV4T]> {
+ let isTaken = isTak;
let isPredicatedFalse = isNegCond;
let isBrTaken = !if(isTaken, "true", "false");
let Inst{25-23} = majOp;
let Inst{22} = isNegCond;
let Inst{18-16} = src1;
- let Inst{13} = isTaken;
+ let Inst{13} = isTak;
let Inst{12-8} = src2;
let Inst{21-20} = offset{10-9};
let Inst{7-1} = offset{8-2};
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
- bit isNegCond, bit isTaken>
+ bit isNegCond, bit isTak>
: NVInst_V4<(outs),
(ins IntRegs:$src1, brtarget:$offset),
"if ("#!if(isNegCond, "!","")#mnemonic
#"($src1.new, #"#ImmVal#")) jump:"
- #!if(isTaken, "t","nt")#" $offset",
+ #!if(isTak, "t","nt")#" $offset",
[]>, Requires<[HasV4T]> {
+ let isTaken = isTak;
let isPredicatedFalse = isNegCond;
let isBrTaken = !if(isTaken, "true", "false");
let Inst{25-23} = majOp;
let Inst{22} = isNegCond;
let Inst{18-16} = src1;
- let Inst{13} = isTaken;
+ let Inst{13} = isTak;
let Inst{21-20} = offset{10-9};
let Inst{7-1} = offset{8-2};
}
// mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
let AddedComplexity = 225 in
- def : Pat <(stOp (OpNode (ldOp addrPred:$addr), immPred:$bitend),
- addrPred:$addr),
- (MI IntRegs:$addr, #0, (xformFunc immPred:$bitend))>;
+ def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
+ immPred:$bitend),
+ (addrPred (i32 IntRegs:$addr), extPred:$offset)),
+ (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
}
multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
let AddedComplexity = 141 in
// mem[bhw](Rs+#0) [+-&|]= Rt
- def : Pat <(stOp (OpNode (ldOp addrPred:$addr), (i32 IntRegs:$addend)),
- addrPred:$addr),
- (MI IntRegs:$addr, #0, (i32 IntRegs:$addend) )>;
+ def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
+ (i32 IntRegs:$addend)),
+ (addrPred (i32 IntRegs:$addr), extPred:$offset)),
+ (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
// mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
let AddedComplexity = 150 in