Lift alignment restrictions on load folding for a significant portion of AVX instruct...

[oota-llvm.git] / lib / Target / Hexagon / HexagonMachineScheduler.h

diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.h b/lib/Target/Hexagon/HexagonMachineScheduler.h
index 5b6f226a00e53d121d26483ae9d292e5028f5c8d..8ac333fa7db312d15c3aca8a5d8a8412a673bc4b 100644 (file)
--- a/lib/Target/Hexagon/HexagonMachineScheduler.h
+++ b/lib/Target/Hexagon/HexagonMachineScheduler.h
@@ -14,6 +14,9 @@
 #ifndef HEXAGONASMPRINTER_H
 #define HEXAGONASMPRINTER_H
 
+#include "llvm/ADT/OwningPtr.h"
+#include "llvm/ADT/PriorityQueue.h"
+#include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
 #include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/CodeGen/Passes.h"
@@ -22,14 +25,11 @@
 #include "llvm/CodeGen/ResourcePriorityQueue.h"
 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
-#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/OwningPtr.h"
-#include "llvm/ADT/PriorityQueue.h"
+#include "llvm/Target/TargetInstrInfo.h"
 
 using namespace llvm;
 
@@ -45,7 +45,7 @@ class VLIWResourceModel {
   /// definition of DFA by a target.
   DFAPacketizer *ResourcesModel;
 
-  const InstrItineraryData *InstrItins;
+  const TargetSchedModel *SchedModel;
 
   /// Local packet/bundle model. Purely
   /// internal to the MI schedulre at the time.
@@ -55,29 +55,15 @@ class VLIWResourceModel {
   unsigned TotalPackets;
 
 public:
-  VLIWResourceModel(MachineSchedContext *C, const InstrItineraryData *IID) :
-    InstrItins(IID), TotalPackets(0) {
-    const TargetMachine &TM = C->MF->getTarget();
-    ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
-
-    // This hard requirement could be relaxed,
-    // but for now do not let it proceed.
-    assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
-
-    Packet.resize(InstrItins->SchedModel->IssueWidth);
-    Packet.clear();
-    ResourcesModel->clearResources();
-  }
-
-  VLIWResourceModel(const TargetMachine &TM) :
-    InstrItins(TM.getInstrItineraryData()), TotalPackets(0) {
+VLIWResourceModel(const TargetMachine &TM, const TargetSchedModel *SM) :
+    SchedModel(SM), TotalPackets(0) {
     ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
 
     // This hard requirement could be relaxed,
     // but for now do not let it proceed.
     assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
 
-    Packet.resize(InstrItins->SchedModel->IssueWidth);
+    Packet.resize(SchedModel->getIssueWidth());
     Packet.clear();
     ResourcesModel->clearResources();
   }
@@ -146,6 +132,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
   /// of "hazards" and other interlocks at the current cycle.
   struct SchedBoundary {
     VLIWMachineScheduler *DAG;
+    const TargetSchedModel *SchedModel;
 
     ReadyQueue Available;
     ReadyQueue Pending;
@@ -166,7 +153,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
     /// Pending queues extend the ready queues with the same ID and the
     /// PendingFlag set.
     SchedBoundary(unsigned ID, const Twine &Name):
-      DAG(0), Available(ID, Name+".A"),
+      DAG(0), SchedModel(0), Available(ID, Name+".A"),
       Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P"),
       CheckPending(false), HazardRec(0), ResourceModel(0),
       CurrCycle(0), IssueCount(0),
@@ -177,6 +164,11 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
       delete HazardRec;
     }
 
+    void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
+      DAG = dag;
+      SchedModel = smodel;
+    }
+
     bool isTop() const {
       return Available.getID() == ConvergingVLIWScheduler::TopQID;
     }
@@ -197,7 +189,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
   };
 
   VLIWMachineScheduler *DAG;
-  const TargetRegisterInfo *TRI;
+  const TargetSchedModel *SchedModel;
 
   // State of the top and bottom scheduled instruction boundaries.
   SchedBoundary Top;
@@ -212,7 +204,7 @@ public:
   };
 
   ConvergingVLIWScheduler():
-    DAG(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
+    DAG(0), SchedModel(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
 
   virtual void initialize(ScheduleDAGMI *dag);
 
@@ -241,7 +233,7 @@ protected:
                                SchedCandidate &Candidate);
 #ifndef NDEBUG
   void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
-                      PressureElement P = PressureElement());
+                      PressureChange P = PressureChange());
 #endif
 };