FrameLowering(Subtarget),
InstrItins(&Subtarget.getInstrItineraryData()) {
setMCUseCFI(false);
+ initAsmInfo();
}
// addPassesForOptimizations - Allow the backend (target) to add Target
public:
HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {
- // Enable MI scheduler.
- if (!DisableHexagonMISched) {
+ // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define
+ // HexagonSubtarget::enableMachineScheduler() { return true; }.
+ // That will bypass the SelectionDAG VLIW scheduler, which is probably just
+ // hurting compile time and will be removed eventually anyway.
+ if (DisableHexagonMISched)
+ disablePass(&MachineSchedulerID);
+ else
enablePass(&MachineSchedulerID);
- MachineSchedRegistry::setDefault(createVLIWMachineSched);
- }
}
HexagonTargetMachine &getHexagonTargetMachine() const {
return getTM<HexagonTargetMachine>();
}
+ virtual ScheduleDAGInstrs *
+ createMachineScheduler(MachineSchedContext *C) const {
+ return createVLIWMachineSched(C);
+ }
+
virtual bool addInstSelector();
virtual bool addPreRegAlloc();
virtual bool addPostRegAlloc();
}
bool HexagonPassConfig::addInstSelector() {
- const HexagonTargetMachine &TM = getHexagonTargetMachine();
+ HexagonTargetMachine &TM = getHexagonTargetMachine();
bool NoOpt = (getOptLevel() == CodeGenOpt::None);
if (!NoOpt)
bool HexagonPassConfig::addPreSched2() {
const HexagonTargetMachine &TM = getHexagonTargetMachine();
- HexagonTargetObjectFile &TLOF =
- (HexagonTargetObjectFile&)(getTargetLowering()->getObjFileLowering());
+ const HexagonTargetObjectFile &TLOF =
+ (const HexagonTargetObjectFile &)getTargetLowering()->getObjFileLowering();
+ addPass(createHexagonCopyToCombine());
if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID);
if (!TLOF.IsSmallDataEnabled()) {
printAndVerify("After hexagon split const32/64 pass");
}
return true;
- if (getOptLevel() != CodeGenOpt::None)
- addPass(&IfConverterID);
- return false;
}
bool HexagonPassConfig::addPreEmitPass() {