unsigned DepReg) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
- const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo* QRI =
+ (const HexagonRegisterInfo *) TM.getRegisterInfo();
// Check for lr dependence
if (DepReg == QRI->getRARegister()) {
// Check if this is a predicate dependence
const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
- if (RC == Hexagon::PredRegsRegisterClass) {
+ if (RC == &Hexagon::PredRegsRegClass) {
return true;
}
// to the new-value stores.
bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
- const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo* QRI =
+ (const HexagonRegisterInfo *) TM.getRegisterInfo();
switch (MI->getOpcode())
{
// store byte
static int GetDotNewOp(const int opc) {
switch (opc) {
default: llvm_unreachable("Unknown .new type");
-
// store new value byte
case Hexagon::STrib:
return Hexagon::STrib_nv_V4;
static int GetDotNewPredOp(const int opc) {
switch (opc) {
default: llvm_unreachable("Unknown .new type");
-
// Conditional stores
// Store byte conditionally
case Hexagon::STrib_cPt :
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
int NewOpcode;
- if (RC == Hexagon::PredRegsRegisterClass)
+ if (RC == &Hexagon::PredRegsRegClass)
NewOpcode = GetDotNewPredOp(MI->getOpcode());
else
NewOpcode = GetDotNewOp(MI->getOpcode());
static int GetDotOldOp(const int opc) {
switch (opc) {
default: llvm_unreachable("Unknown .old type");
-
case Hexagon::TFR_cdnPt:
return Hexagon::TFR_cPt;
const HexagonInstrInfo *QII) {
switch (MI->getOpcode()) {
+ default: llvm_unreachable("Unknown predicate sense of the instruction");
case Hexagon::TFR_cPt:
case Hexagon::TFR_cdnPt:
case Hexagon::TFRI_cPt:
case Hexagon::STh_GP_cdnNotPt_V4 :
case Hexagon::STw_GP_cdnNotPt_V4 :
return false;
-
- default:
- assert (false && "Unknown predicate sense of the instruction");
}
// return *some value* to avoid compiler warning
return false;
case Hexagon::STh_GP_cdnNotPt_V4:
case Hexagon::STw_GP_cdnPt_V4:
case Hexagon::STw_GP_cdnNotPt_V4:
-
return true;
}
return false;
GetStoreValueOperand(MI).getReg() != DepReg)
return false;
- const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo* QRI =
+ (const HexagonRegisterInfo *) TM.getRegisterInfo();
const MCInstrDesc& MCID = PacketMI->getDesc();
// first operand is always the result
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
- const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI);
+ const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
// if there is already an store in the packet, no can do new value store
// Arch Spec 3.4.4.2.
return false;
}
- if (PacketRC == Hexagon::DoubleRegsRegisterClass) {
+ if (PacketRC == &Hexagon::DoubleRegsRegClass) {
// new value store constraint: double regs can not feed into new value store
// arch spec section: 5.4.2.2
return false;
return false;
}
- // If the source that feeds the store is predicated, new value store must also be
- // also predicated.
+ // If the source that feeds the store is predicated, new value store must
+ // also be also predicated.
if (QII->isPredicated(PacketMI)) {
if (!QII->isPredicated(MI))
return false;
// Check to make sure that they both will have their predicates
// evaluate identically
- unsigned predRegNumSrc;
- unsigned predRegNumDst;
- const TargetRegisterClass* predRegClass;
+ unsigned predRegNumSrc = 0;
+ unsigned predRegNumDst = 0;
+ const TargetRegisterClass* predRegClass = NULL;
// Get predicate register used in the source instruction
for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
if ( PacketMI->getOperand(opNum).isReg())
predRegNumSrc = PacketMI->getOperand(opNum).getReg();
predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
- if (predRegClass == Hexagon::PredRegsRegisterClass) {
+ if (predRegClass == &Hexagon::PredRegsRegClass) {
break;
}
}
- assert ((predRegClass == Hexagon::PredRegsRegisterClass ) &&
+ assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
("predicate register not found in a predicated PacketMI instruction"));
// Get predicate register used in new-value store instruction
if ( MI->getOperand(opNum).isReg())
predRegNumDst = MI->getOperand(opNum).getReg();
predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
- if (predRegClass == Hexagon::PredRegsRegisterClass) {
+ if (predRegClass == &Hexagon::PredRegsRegClass) {
break;
}
}
- assert ((predRegClass == Hexagon::PredRegsRegisterClass ) &&
+ assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
("predicate register not found in a predicated MI instruction"));
// New-value register producer and user (store) need to satisfy these
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
if (MI->getOperand(opNum).isReg() &&
- TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(), QRI))
+ TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
+ QRI))
return false;
}
}
MachineBasicBlock::iterator &MII)
{
- const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo* QRI =
+ (const HexagonRegisterInfo *) TM.getRegisterInfo();
if (!QRI->Subtarget.hasV4TOps() ||
!IsNewifyStore(MI))
return false;
return false;
// predicate .new
- if (RC == Hexagon::PredRegsRegisterClass && isCondInst(MI))
+ if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
return true;
- else if (RC != Hexagon::PredRegsRegisterClass &&
+ else if (RC != &Hexagon::PredRegsRegClass &&
!IsNewifyStore(MI)) // MI is not a new-value store
return false;
else {
int NewOpcode = GetDotNewOp(MI->getOpcode());
const MCInstrDesc &desc = QII->get(NewOpcode);
DebugLoc dl;
- MachineInstr *NewMI = MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
+ MachineInstr *NewMI =
+ MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
// there already exist anti dep on the same pred in
// the packet.
if (PacketSU->Succs[i].getSUnit() == SU &&
- Hexagon::PredRegsRegisterClass->contains(
+ Hexagon::PredRegsRegClass.contains(
PacketSU->Succs[i].getReg()) &&
PacketSU->Succs[i].getKind() == SDep::Data &&
// Here I know that *VIN is predicate setting instruction
// If it doesn't, we ignore the instruction.
const MCInstrDesc& TID = MI->getDesc();
unsigned SchedClass = TID.getSchedClass();
- const InstrStage* IS = ResourceTracker->getInstrItins()->beginStage(SchedClass);
+ const InstrStage* IS =
+ ResourceTracker->getInstrItins()->beginStage(SchedClass);
unsigned FuncUnits = IS->getUnits();
return !FuncUnits;
}
MachineBasicBlock::iterator II = I;
const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
- const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo* QRI =
+ (const HexagonRegisterInfo *) TM.getRegisterInfo();
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
// Inline asm cannot go in the packet.
return true;
}
-MachineBasicBlock::iterator HexagonPacketizerList::addToPacket(MachineInstr *MI) {
+MachineBasicBlock::iterator
+HexagonPacketizerList::addToPacket(MachineInstr *MI) {
MachineBasicBlock::iterator MII = MI;
MachineBasicBlock *MBB = MI->getParent();
&& (!tryAllocateResourcesForConstExt(nvjMI)
|| !ResourceTracker->canReserveResources(nvjMI)))
|| // For non-extended instruction, no need to allocate extra 4 bytes.
- (!QII->isExtended(nvjMI) && !ResourceTracker->canReserveResources(nvjMI)))
+ (!QII->isExtended(nvjMI) &&
+ !ResourceTracker->canReserveResources(nvjMI)))
{
endPacket(MBB, MI);
// A new and empty packet starts.