simplify some code and eliminate the symbolicAddressesAreRIPRel() predicate.

[oota-llvm.git] / lib / Target / IA64 / IA64Bundling.cpp

diff --git a/lib/Target/IA64/IA64Bundling.cpp b/lib/Target/IA64/IA64Bundling.cpp
index 2f3d238f082d6d5c0f8b56d6f81f1e7567066f78..3a9ba6ca3f617e0ccd1c5268f39208cd30c23dde 100644 (file)
--- a/lib/Target/IA64/IA64Bundling.cpp
+++ b/lib/Target/IA64/IA64Bundling.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Duraid Madina and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -20,26 +20,30 @@
 // 
 //===----------------------------------------------------------------------===//
 
+#define DEBUG_TYPE "ia64-codegen"
 #include "IA64.h"
+#include "IA64InstrInfo.h"
+#include "IA64TargetMachine.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/ADT/SetOperations.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Support/Debug.h"
 #include <set>
-#include <iostream>
 using namespace llvm;
 
-namespace {
-  Statistic<> StopBitsAdded("ia64-codegen", "Number of stop bits added");
+STATISTIC(StopBitsAdded, "Number of stop bits added");
 
+namespace {
   struct IA64BundlingPass : public MachineFunctionPass {
+    static char ID;
     /// Target machine description which we query for reg. names, data
     /// layout, etc.
     ///
-    TargetMachine &TM;
+    IA64TargetMachine &TM;
 
-    IA64BundlingPass(TargetMachine &tm) : TM(tm) { }
+    IA64BundlingPass(IA64TargetMachine &tm) 
+      : MachineFunctionPass(&ID), TM(tm) { }
 
     virtual const char *getPassName() const {
       return "IA64 (Itanium) Bundling Pass";
@@ -54,17 +58,18 @@ namespace {
       return Changed;
     }
 
-    std::set<unsigned> PendingRegWrites; // XXX: ugly global, but
-                         // pending writes can cross basic blocks. Note that
-                         // taken branches end instruction groups. So we
-                        // only need to worry about 'fallthrough' code
+    // XXX: ugly global, but pending writes can cross basic blocks. Note that
+    // taken branches end instruction groups. So we only need to worry about
+    // 'fallthrough' code
+    std::set<unsigned> PendingRegWrites;
   };
+  char IA64BundlingPass::ID = 0;
 } // end of anonymous namespace
 
 /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
 /// and arranges the result into bundles.
 ///
-FunctionPass *llvm::createIA64BundlingPass(TargetMachine &tm) {
+FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) {
   return new IA64BundlingPass(tm);
 }
 
@@ -79,7 +84,7 @@ bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
 
     for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
       MachineOperand &MO=CurrentInsn->getOperand(i);
-      if(MO.isRegister()) {
+      if (MO.isReg()) {
         if(MO.isUse()) { // TODO: exclude p0
           CurrentReads.insert(MO.getReg());
         }
@@ -99,7 +104,8 @@ bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
     
     if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
       // there is a conflict, insert a stop and reset PendingRegWrites
-      CurrentInsn = BuildMI(MBB, CurrentInsn, IA64::STOP, 0);
+      CurrentInsn = BuildMI(MBB, CurrentInsn, CurrentInsn->getDebugLoc(),
+                            TM.getInstrInfo()->get(IA64::STOP), 0);
       PendingRegWrites=OrigWrites; // carry over current writes to next insn
       Changed=true; StopBitsAdded++; // update stats      
     } else { // otherwise, track additional pending writes