#include "llvm/GlobalValue.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
+#include <iostream>
+#include <set>
using namespace llvm;
namespace {
IA64TargetLowering IA64Lowering;
unsigned GlobalBaseReg;
public:
- IA64DAGToDAGISel(TargetMachine &TM)
- : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
+ IA64DAGToDAGISel(IA64TargetMachine &TM)
+ : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- SDOperand Select(SDOperand Op);
+ void Select(SDOperand &Result, SDOperand N);
SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
unsigned OCHi, unsigned OCLo,
#include "IA64GenDAGISel.inc"
private:
- SDOperand SelectCALL(SDOperand Op);
+ SDOperand SelectDIV(SDOperand Op);
};
}
}
// Finally, legalize this node.
- Select(Node);
+ SDOperand Dummy;
+ Select(Dummy, Node);
}
// Select target instructions for the DAG.
- DAG.setRoot(Select(DAG.getRoot()));
+ DAG.setRoot(SelectRoot(DAG.getRoot()));
CodeGenMap.clear();
DAG.RemoveDeadNodes();
ScheduleAndEmitDAG(DAG);
}
-
-SDOperand IA64DAGToDAGISel::SelectCALL(SDOperand Op) {
+SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
SDNode *N = Op.Val;
- SDOperand Chain = Select(N->getOperand(0));
-
- unsigned CallOpcode;
- std::vector<SDOperand> CallOperands;
-
- // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
- SDOperand GPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r1, MVT::i64);
- Chain = GPBeforeCall.getValue(1);
- SDOperand SPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
- Chain = SPBeforeCall.getValue(1);
- SDOperand RPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::rp, MVT::i64);
- Chain = RPBeforeCall.getValue(1);
-
- // if we can call directly, do so
- if (GlobalAddressSDNode *GASD =
- dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
- CallOpcode = IA64::BRCALL_IPREL;
- CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
- MVT::i64));
- } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
- // case for correctness, to avoid
- // "non-pic code with imm reloc.n
- // against dynamic symbol" errors
- dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
- CallOpcode = IA64::BRCALL_IPREL;
- CallOperands.push_back(N->getOperand(1));
- } else {
- // otherwise we need to load the function descriptor,
- // load the branch target (function)'s entry point and GP,
- // branch (call) then restore the
- // GP
-
- SDOperand FnDescriptor = Select(N->getOperand(1));
-
- // load the branch target's entry point [mem] and
- // GP value [mem+8]
- SDOperand targetEntryPoint=CurDAG->getLoad(MVT::i64, Chain, FnDescriptor,
- CurDAG->getSrcValue(0));
- SDOperand targetGPAddr=CurDAG->getNode(ISD::ADD, MVT::i64, FnDescriptor,
- CurDAG->getConstant(8, MVT::i64));
- SDOperand targetGP=CurDAG->getLoad(MVT::i64, Chain, targetGPAddr,
- CurDAG->getSrcValue(0));
-
- // Copy the callee address into the b6 branch register
- SDOperand B6 = CurDAG->getRegister(IA64::B6, MVT::i64);
- Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, B6,
- targetEntryPoint);
+ SDOperand Chain, Tmp1, Tmp2;
+ Select(Chain, N->getOperand(0));
+
+ Select(Tmp1, N->getOperand(0));
+ Select(Tmp2, N->getOperand(1));
+
+ bool isFP=false;
+
+ if(MVT::isFloatingPoint(Tmp1.getValueType()))
+ isFP=true;
- CallOperands.push_back(B6);
- CallOpcode = IA64::BRCALL_INDIRECT;
+ bool isModulus=false; // is it a division or a modulus?
+ bool isSigned=false;
+
+ switch(N->getOpcode()) {
+ case ISD::FDIV:
+ case ISD::SDIV: isModulus=false; isSigned=true; break;
+ case ISD::UDIV: isModulus=false; isSigned=false; break;
+ case ISD::FREM:
+ case ISD::SREM: isModulus=true; isSigned=true; break;
+ case ISD::UREM: isModulus=true; isSigned=false; break;
}
-
- // TODO: support in-memory arguments
- unsigned used_FPArgs=0; // how many FP args have been used so far?
- unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
- IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
- unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
- IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
+ // TODO: check for integer divides by powers of 2 (or other simple patterns?)
- SDOperand InFlag; // Null incoming flag value.
-
- for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
- unsigned DestReg = 0;
- MVT::ValueType RegTy = N->getOperand(i).getValueType();
- if (RegTy == MVT::i64) {
- assert((i-2) < 8 && "Too many int args");
- DestReg = intArgs[i-2];
- } else {
- assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
- "Unpromoted integer arg?");
- assert(used_FPArgs < 8 && "Too many fp args");
- DestReg = FPArgs[used_FPArgs++];
- }
+ SDOperand TmpPR, TmpPR2;
+ SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
+ SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
+ SDNode *Result;
+
+ // we'll need copies of F0 and F1
+ SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
+ SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
- if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
- SDOperand Val = Select(N->getOperand(i));
- Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
- InFlag = Chain.getValue(1);
- CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
+ // OK, emit some code:
+
+ if(!isFP) {
+ // first, load the inputs into FP regs.
+ TmpF1 =
+ SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
+ Chain = TmpF1.getValue(1);
+ TmpF2 =
+ SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
+ Chain = TmpF2.getValue(1);
+
+ // next, convert the inputs to FP
+ if(isSigned) {
+ TmpF3 =
+ SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
+ Chain = TmpF3.getValue(1);
+ TmpF4 =
+ SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
+ Chain = TmpF4.getValue(1);
+ } else { // is unsigned
+ TmpF3 =
+ SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
+ Chain = TmpF3.getValue(1);
+ TmpF4 =
+ SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
+ Chain = TmpF4.getValue(1);
+ }
+
+ } else { // this is an FP divide/remainder, so we 'leak' some temp
+ // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
+ TmpF3=Tmp1;
+ TmpF4=Tmp2;
}
- }
-
- // Finally, once everything is in registers to pass to the call, emit the
- // call itself.
- if (InFlag.Val)
- CallOperands.push_back(InFlag); // Strong dep on register copies.
- else
- CallOperands.push_back(Chain); // Weak dep on whatever occurs before
- Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
- CallOperands);
-
-// return Chain; // HACK: err, this means that functions never return anything. need to intergrate this with the code immediately below FIXME XXX
- std::vector<SDOperand> CallResults;
-
- // If the call has results, copy the values out of the ret val registers.
- switch (N->getValueType(0)) {
- default: assert(0 && "Unexpected ret value!");
- case MVT::Other: break;
- case MVT::i64:
- Chain = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- break;
- case MVT::f64:
- Chain = CurDAG->getCopyFromReg(Chain, IA64::F8, N->getValueType(0),
- Chain.getValue(1)).getValue(1);
- CallResults.push_back(Chain.getValue(0));
- break;
- }
- // restore GP, SP and RP
- Chain = CurDAG->getCopyToReg(Chain, IA64::r1, GPBeforeCall);
- Chain = CurDAG->getCopyToReg(Chain, IA64::r12, SPBeforeCall);
- Chain = CurDAG->getCopyToReg(Chain, IA64::rp, RPBeforeCall);
+ // we start by computing an approximate reciprocal (good to 9 bits?)
+ // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
+ if(isFP)
+ TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
+ TmpF3, TmpF4), 0);
+ else
+ TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
+ TmpF3, TmpF4), 0);
+
+ TmpPR = TmpF5.getValue(1);
+ Chain = TmpF5.getValue(2);
+
+ SDOperand minusB;
+ if(isModulus) { // for remainders, it'll be handy to have
+ // copies of -input_b
+ minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
+ CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
+ Chain = minusB.getValue(1);
+ }
+
+ SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
+
+ TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpF4, TmpF5, F1, TmpPR), 0);
+ Chain = TmpE0.getValue(1);
+ TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF5, TmpE0, TmpF5, TmpPR), 0);
+ Chain = TmpY1.getValue(1);
+ TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpE0, TmpE0, F0, TmpPR), 0);
+ Chain = TmpE1.getValue(1);
+ TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpY1, TmpE1, TmpY1, TmpPR), 0);
+ Chain = TmpY2.getValue(1);
+
+ if(isFP) { // if this is an FP divide, we finish up here and exit early
+ if(isModulus)
+ assert(0 && "Sorry, try another FORTRAN compiler.");
- CallResults.push_back(Chain);
+ SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
+
+ TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpE1, TmpE1, F0, TmpPR), 0);
+ Chain = TmpE2.getValue(1);
+ TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpY2, TmpE2, TmpY2, TmpPR), 0);
+ Chain = TmpY3.getValue(1);
+ TmpQ0 =
+ SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
+ Tmp1, TmpY3, F0, TmpPR), 0);
+ Chain = TmpQ0.getValue(1);
+ TmpR0 =
+ SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
+ Tmp2, TmpQ0, Tmp1, TmpPR), 0);
+ Chain = TmpR0.getValue(1);
+
+// we want Result to have the same target register as the frcpa, so
+// we two-address hack it. See the comment "for this to work..." on
+// page 48 of Intel application note #245415
+ Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
+ TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
+ Chain = SDOperand(Result, 1);
+ return SDOperand(Result, 0); // XXX: early exit!
+ } else { // this is *not* an FP divide, so there's a bit left to do:
+
+ SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
+
+ TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpF3, TmpY2, F0, TmpPR), 0);
+ Chain = TmpQ2.getValue(1);
+ TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpF4, TmpQ2, TmpF3, TmpPR), 0);
+ Chain = TmpR2.getValue(1);
+
+// we want TmpQ3 to have the same target register as the frcpa? maybe we
+// should two-address hack it. See the comment "for this to work..." on page
+// 48 of Intel application note #245415
+ TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
+ TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0);
+ Chain = TmpQ3.getValue(1);
+
+ // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
+ // the FPSWA won't be able to help out in the case of large/tiny
+ // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
+
+ if(isSigned)
+ TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
+ MVT::f64, TmpQ3), 0);
+ else
+ TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
+ MVT::f64, TmpQ3), 0);
+
+ Chain = TmpQ.getValue(1);
+
+ if(isModulus) {
+ SDOperand FPminusB =
+ SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
+ Chain = FPminusB.getValue(1);
+ SDOperand Remainder =
+ SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
+ TmpQ, FPminusB, TmpF1), 0);
+ Chain = Remainder.getValue(1);
+ Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
+ Chain = SDOperand(Result, 1);
+ } else { // just an integer divide
+ Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
+ Chain = SDOperand(Result, 1);
+ }
- for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
- CodeGenMap[Op.getValue(i)] = CallResults[i];
-
- return CallResults[Op.ResNo];
+ return SDOperand(Result, 0);
+ } // wasn't an FP divide
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
+void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
- N->getOpcode() < IA64ISD::FIRST_NUMBER)
- return Op; // Already selected.
+ N->getOpcode() < IA64ISD::FIRST_NUMBER) {
+ Result = Op;
+ return; // Already selected.
+ }
// If this has already been converted, use it.
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
- if (CGMI != CodeGenMap.end()) return CGMI->second;
+ if (CGMI != CodeGenMap.end()) {
+ Result = CGMI->second;
+ return;
+ }
switch (N->getOpcode()) {
default: break;
- case ISD::CALL:
- case ISD::TAILCALL: return SelectCALL(Op);
+ case IA64ISD::BRCALL: { // XXX: this is also a hack!
+ SDOperand Chain;
+ SDOperand InFlag; // Null incoming flag value.
+
+ Select(Chain, N->getOperand(0));
+ if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
+ Select(InFlag, N->getOperand(2));
+
+ unsigned CallOpcode;
+ SDOperand CallOperand;
+
+ // if we can call directly, do so
+ if (GlobalAddressSDNode *GASD =
+ dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
+ CallOpcode = IA64::BRCALL_IPREL_GA;
+ CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
+ } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
+ // case for correctness, to avoid
+ // "non-pic code with imm reloc.n
+ // against dynamic symbol" errors
+ dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
+ CallOpcode = IA64::BRCALL_IPREL_ES;
+ CallOperand = N->getOperand(1);
+ } else {
+ // otherwise we need to load the function descriptor,
+ // load the branch target (function)'s entry point and GP,
+ // branch (call) then restore the GP
+ SDOperand FnDescriptor;
+ Select(FnDescriptor, N->getOperand(1));
+
+ // load the branch target's entry point [mem] and
+ // GP value [mem+8]
+ SDOperand targetEntryPoint=
+ SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
+ Chain = targetEntryPoint.getValue(1);
+ SDOperand targetGPAddr=
+ SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
+ FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
+ Chain = targetGPAddr.getValue(1);
+ SDOperand targetGP=
+ SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
+ Chain = targetGP.getValue(1);
+
+ Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
+ InFlag = Chain.getValue(1);
+ Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
+ InFlag = Chain.getValue(1);
+
+ CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
+ CallOpcode = IA64::BRCALL_INDIRECT;
+ }
-/* todo:
- * case ISD::DYNAMIC_STACKALLOC:
-*/
+ // Finally, once everything is setup, emit the call itself
+ if(InFlag.Val)
+ Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
+ CallOperand, InFlag), 0);
+ else // there might be no arguments
+ Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
+ CallOperand, Chain), 0);
+ InFlag = Chain.getValue(1);
+
+ std::vector<SDOperand> CallResults;
+
+ CallResults.push_back(Chain);
+ CallResults.push_back(InFlag);
+
+ for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
+ CodeGenMap[Op.getValue(i)] = CallResults[i];
+ Result = CallResults[Op.ResNo];
+ return;
+ }
+
+ case IA64ISD::GETFD: {
+ SDOperand Input;
+ Select(Input, N->getOperand(0));
+ Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
+ CodeGenMap[Op] = Result;
+ return;
+ }
+
+ case ISD::FDIV:
+ case ISD::SDIV:
+ case ISD::UDIV:
+ case ISD::SREM:
+ case ISD::UREM:
+ Result = SelectDIV(Op);
+ return;
+
+ case ISD::TargetConstantFP: {
+ SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
+
+ if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
+ Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
+ } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
+ Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
+ } else
+ assert(0 && "Unexpected FP constant!");
+ return;
+ }
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- if (N->hasOneUse()) {
- CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64));
- return SDOperand(N, 0);
- }
- return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64));
+ if (N->hasOneUse())
+ Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
+ else
+ Result = CodeGenMap[Op] = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
+ return;
+ }
+
+ case ISD::ConstantPool: { // TODO: nuke the constant pool
+ // (ia64 doesn't need one)
+ ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
+ Constant *C = CP->get();
+ SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
+ CP->getAlignment());
+ Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
+ CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
+ return;
}
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
- SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
- CurDAG->getRegister(IA64::r1, MVT::i64), GA);
- return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
+ SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
+ CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
+ Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
+ return;
}
-
+
+/* XXX case ISD::ExternalSymbol: {
+ SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
+ MVT::i64);
+ SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
+ CurDAG->getRegister(IA64::r1, MVT::i64), EA);
+ return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
+ }
+*/
+
case ISD::LOAD:
- case ISD::EXTLOAD:
+ case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
case ISD::ZEXTLOAD: {
- SDOperand Chain = Select(N->getOperand(0));
- SDOperand Address = Select(N->getOperand(1));
+ SDOperand Chain, Address;
+ Select(Chain, N->getOperand(0));
+ Select(Address, N->getOperand(1));
MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
unsigned Opc;
switch (TypeBeingLoaded) {
default: N->dump(); assert(0 && "Cannot load this type!");
- // FIXME: bools? case MVT::i1:
+ case MVT::i1: { // this is a bool
+ Opc = IA64::LD1; // first we load a byte, then compare for != 0
+ if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
+ Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+ SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
+ CurDAG->getRegister(IA64::r0, MVT::i64),
+ Chain).getValue(Op.ResNo);
+ return;
+ }
+ /* otherwise, we want to load a bool into something bigger: LD1
+ will do that for us, so we just fall through */
+ }
case MVT::i8: Opc = IA64::LD1; break;
case MVT::i16: Opc = IA64::LD2; break;
case MVT::i32: Opc = IA64::LD4; break;
case MVT::f64: Opc = IA64::LDF8; break;
}
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
- Address, Chain); // TODO: comment this
-
- return SDOperand(N, Op.ResNo);
+ // TODO: comment this
+ Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+ Address, Chain).getValue(Op.ResNo);
+ return;
}
case ISD::TRUNCSTORE:
case ISD::STORE: {
- SDOperand Address = Select(N->getOperand(2));
-
+ SDOperand Address, Chain;
+ Select(Address, N->getOperand(2));
+ Select(Chain, N->getOperand(0));
+
unsigned Opc;
if (N->getOpcode() == ISD::STORE) {
switch (N->getOperand(1).getValueType()) {
- default: assert(0 && "unknown Type in store");
+ default: assert(0 && "unknown type in store");
+ case MVT::i1: { // this is a bool
+ Opc = IA64::ST1; // we store either 0 or 1 as a byte
+ // first load zero!
+ SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
+ Chain = Initial.getValue(1);
+ // then load 1 into the same reg iff the predicate to store is 1
+ SDOperand Tmp;
+ Select(Tmp, N->getOperand(1));
+ Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
+ CurDAG->getConstant(1, MVT::i64),
+ Tmp), 0);
+ Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
+ return;
+ }
case MVT::i64: Opc = IA64::ST8; break;
case MVT::f64: Opc = IA64::STF8; break;
- }
+ }
} else { //ISD::TRUNCSTORE
switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
- default: assert(0 && "unknown Type in store");
+ default: assert(0 && "unknown type in truncstore");
case MVT::i8: Opc = IA64::ST1; break;
case MVT::i16: Opc = IA64::ST2; break;
case MVT::i32: Opc = IA64::ST4; break;
}
}
- CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
- Select(N->getOperand(1)), Select(N->getOperand(0)));
- return SDOperand(N, 0);
+ SDOperand N1, N2;
+ Select(N1, N->getOperand(1));
+ Select(N2, N->getOperand(2));
+ Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
+ return;
}
case ISD::BRCOND: {
- SDOperand Chain = Select(N->getOperand(0));
- SDOperand CC = Select(N->getOperand(1));
+ SDOperand Chain, CC;
+ Select(Chain, N->getOperand(0));
+ Select(CC, N->getOperand(1));
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
- CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, CurDAG->getBasicBlock(Dest), Chain);
- return SDOperand(N, 0);
+ Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
+ CurDAG->getBasicBlock(Dest), Chain);
+ return;
}
case ISD::CALLSEQ_START:
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
- CurDAG->SelectNodeTo(N, Opc, MVT::Other,
- getI64Imm(Amt), Select(N->getOperand(0)));
- return SDOperand(N, 0);
+ SDOperand N0;
+ Select(N0, N->getOperand(0));
+ Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
+ return;
}
- case ISD::RET: {
- SDOperand Chain = Select(N->getOperand(0)); // Token chain.
-
- switch (N->getNumOperands()) {
- default:
- assert(0 && "Unknown return instruction!");
- case 2: {
- SDOperand RetVal = Select(N->getOperand(1));
- switch (RetVal.getValueType()) {
- default: assert(0 && "I don't know how to return this type! (promote?)");
- // FIXME: do I need to add support for bools here?
- // (return '0' or '1' in r8, basically...)
- //
- // FIXME: need to round floats - 80 bits is bad, the tester
- // told me so
- case MVT::i64:
- // we mark r8 as live on exit up above in LowerArguments()
- // BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
- break;
- case MVT::f64:
- // we mark F8 as live on exit up above in LowerArguments()
- // BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
- break;
- }
- break;
- }
- case 1:
- break;
- }
-
- // we need to copy VirtGPR (the vreg (to become a real reg)) that holds
- // the output of this function's alloc instruction back into ar.pfs
- // before we return. this copy must not float up above the last
- // outgoing call in this function!!!
- SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
- MVT::i64);
- Chain = AR_PFSVal.getValue(1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
-
- CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain); // and then just emit a 'ret' instruction
-
- // before returning, restore the ar.pfs register (set by the 'alloc' up top)
- // BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
- //
- return SDOperand(N, 0);
- }
-
case ISD::BR:
// FIXME: we don't need long branches all the time!
- CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, N->getOperand(1),
- Select(N->getOperand(0)));
- return SDOperand(N, 0);
-
+ SDOperand N0;
+ Select(N0, N->getOperand(0));
+ Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
+ N->getOperand(1), N0);
+ return;
}
- return SelectCode(Op);
+ SelectCode(Result, Op);
}
/// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
/// into an IA64-specific DAG, ready for instruction scheduling.
///
-FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
+FunctionPass
+*llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
return new IA64DAGToDAGISel(TM);
}
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