#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
using namespace llvm;
IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
- // register class for general registers
- addRegisterClass(MVT::i64, IA64::GRRegisterClass);
+ // register class for general registers
+ addRegisterClass(MVT::i64, IA64::GRRegisterClass);
- // register class for FP registers
- addRegisterClass(MVT::f64, IA64::FPRegisterClass);
+ // register class for FP registers
+ addRegisterClass(MVT::f64, IA64::FPRegisterClass);
- // register class for predicate registers
- addRegisterClass(MVT::i1, IA64::PRRegisterClass);
+ // register class for predicate registers
+ addRegisterClass(MVT::i1, IA64::PRRegisterClass);
- setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote);
+ setLoadExtAction(ISD::EXTLOAD , MVT::i1 , Promote);
- setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
+ setLoadExtAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
- setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Promote);
- setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand);
- setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
- setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
+ setLoadExtAction(ISD::SEXTLOAD , MVT::i1 , Promote);
+ setLoadExtAction(ISD::SEXTLOAD , MVT::i8 , Expand);
+ setLoadExtAction(ISD::SEXTLOAD , MVT::i16 , Expand);
+ setLoadExtAction(ISD::SEXTLOAD , MVT::i32 , Expand);
- setOperationAction(ISD::BRIND , MVT::Other, Expand);
- setOperationAction(ISD::BR_JT , MVT::Other, Expand);
- setOperationAction(ISD::BR_CC , MVT::Other, Expand);
- setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
+ setOperationAction(ISD::BRIND , MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT , MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC , MVT::Other, Expand);
+ setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
- // ia64 uses SELECT not SELECT_CC
- setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
-
- // We need to handle ISD::RET for void functions ourselves,
- // so we get a chance to restore ar.pfs before adding a
- // br.ret insn
- setOperationAction(ISD::RET, MVT::Other, Custom);
-
- setSetCCResultType(MVT::i1);
- setShiftAmountType(MVT::i64);
-
- setOperationAction(ISD::FREM , MVT::f32 , Expand);
- setOperationAction(ISD::FREM , MVT::f64 , Expand);
-
- setOperationAction(ISD::UREM , MVT::f32 , Expand);
- setOperationAction(ISD::UREM , MVT::f64 , Expand);
-
- setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
- setOperationAction(ISD::MEMSET , MVT::Other, Expand);
- setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
- setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
-
- setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
- setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
-
- // We don't support sin/cos/sqrt/pow
- setOperationAction(ISD::FSIN , MVT::f64, Expand);
- setOperationAction(ISD::FCOS , MVT::f64, Expand);
- setOperationAction(ISD::FSQRT, MVT::f64, Expand);
- setOperationAction(ISD::FPOW , MVT::f64, Expand);
- setOperationAction(ISD::FSIN , MVT::f32, Expand);
- setOperationAction(ISD::FCOS , MVT::f32, Expand);
- setOperationAction(ISD::FSQRT, MVT::f32, Expand);
- setOperationAction(ISD::FPOW , MVT::f32, Expand);
-
- // FIXME: IA64 supports fcopysign natively!
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
-
- // We don't have line number support yet.
- setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
-
- //IA64 has these, but they are not implemented
- setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
- setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
- setOperationAction(ISD::ROTL , MVT::i64 , Expand);
- setOperationAction(ISD::ROTR , MVT::i64 , Expand);
- setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
-
- // VASTART needs to be custom lowered to use the VarArgsFrameIndex
- setOperationAction(ISD::VAARG , MVT::Other, Custom);
- setOperationAction(ISD::VASTART , MVT::Other, Custom);
-
- // Use the default implementation.
- setOperationAction(ISD::VACOPY , MVT::Other, Expand);
- setOperationAction(ISD::VAEND , MVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+ // ia64 uses SELECT not SELECT_CC
+ setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
+
+ // We need to handle ISD::RET for void functions ourselves,
+ // so we get a chance to restore ar.pfs before adding a
+ // br.ret insn
+ setOperationAction(ISD::RET, MVT::Other, Custom);
- // Thread Local Storage
- setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
+ setShiftAmountType(MVT::i64);
- setStackPointerRegisterToSaveRestore(IA64::r12);
+ setOperationAction(ISD::FREM , MVT::f32 , Expand);
+ setOperationAction(ISD::FREM , MVT::f64 , Expand);
- setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
- setJumpBufAlignment(16); // ...and must be 16-byte aligned
-
- computeRegisterProperties();
+ setOperationAction(ISD::UREM , MVT::f32 , Expand);
+ setOperationAction(ISD::UREM , MVT::f64 , Expand);
+
+ setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
+
+ setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
+ setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
+
+ // We don't support sin/cos/sqrt/pow
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+ setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+ setOperationAction(ISD::FPOW , MVT::f32, Expand);
+
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
+
+ // FIXME: IA64 supports fcopysign natively!
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+
+ // We don't have line number support yet.
+ setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+
+ // IA64 has ctlz in the form of the 'fnorm' instruction. The Legalizer
+ // expansion for ctlz/cttz in terms of ctpop is much larger, but lower
+ // latency.
+ // FIXME: Custom lower CTLZ when compiling for size?
+ setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
+ setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
+ setOperationAction(ISD::ROTL , MVT::i64 , Expand);
+ setOperationAction(ISD::ROTR , MVT::i64 , Expand);
+
+ // FIXME: IA64 has this, but is not implemented. should be mux @rev
+ setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
+
+ // VASTART needs to be custom lowered to use the VarArgsFrameIndex
+ setOperationAction(ISD::VAARG , MVT::Other, Custom);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
+
+ // FIXME: These should be legal
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
+
+ // Use the default implementation.
+ setOperationAction(ISD::VACOPY , MVT::Other, Expand);
+ setOperationAction(ISD::VAEND , MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
+ // Thread Local Storage
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
+
+ setStackPointerRegisterToSaveRestore(IA64::r12);
+
+ setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
+ setJumpBufAlignment(16); // ...and must be 16-byte aligned
+
+ computeRegisterProperties();
- addLegalFPImmediate(APFloat(+0.0));
- addLegalFPImmediate(APFloat(-0.0));
- addLegalFPImmediate(APFloat(+1.0));
- addLegalFPImmediate(APFloat(-1.0));
+ addLegalFPImmediate(APFloat(+0.0));
+ addLegalFPImmediate(APFloat(-0.0));
+ addLegalFPImmediate(APFloat(+1.0));
+ addLegalFPImmediate(APFloat(-1.0));
}
const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
+MVT IA64TargetLowering::getSetCCResultType(MVT VT) const {
+ return MVT::i1;
+}
-std::vector<SDOperand>
-IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
- std::vector<SDOperand> ArgValues;
+/// getFunctionAlignment - Return the Log2 alignment of this function.
+unsigned IA64TargetLowering::getFunctionAlignment(const Function *) const {
+ return 5;
+}
+
+void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &ArgValues,
+ DebugLoc dl) {
//
// add beautiful description of IA64 stack frame format
// here (from intel 24535803.pdf most likely)
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
{
- SDOperand newroot, argt;
+ SDValue newroot, argt;
if(count < 8) { // need to fix this logic? maybe.
- switch (getValueType(I->getType())) {
+ switch (getValueType(I->getType()).getSimpleVT()) {
default:
- assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
+ llvm_unreachable("ERROR in LowerArgs: can't lower this type of arg.");
case MVT::f32:
// fixme? (well, will need to for weird FP structy stuff,
// see intel ABI docs)
// FP args go into f8..f15 as needed: (hence the ++)
argPreg[count] = args_FP[used_FPArgs++];
argOpc[count] = IA64::FMOV;
- argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
- MVT::f64);
+ argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), dl,
+ argVreg[count], MVT::f64);
if (I->getType() == Type::FloatTy)
- argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
+ argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt,
DAG.getIntPtrConstant(0));
break;
case MVT::i1: // NOTE: as far as C abi stuff goes,
argPreg[count] = args_int[count];
argOpc[count] = IA64::MOV;
argt = newroot =
- DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
+ DAG.getCopyFromReg(DAG.getRoot(), dl, argVreg[count], MVT::i64);
if ( getValueType(I->getType()) != MVT::i64)
- argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
+ argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()),
newroot);
break;
}
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
- argt = newroot = DAG.getLoad(getValueType(I->getType()),
+ SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
+ argt = newroot = DAG.getLoad(getValueType(I->getType()), dl,
DAG.getEntryNode(), FIN, NULL, 0);
}
++count;
// Create a vreg to hold the output of (what will become)
// the "alloc" instruction
VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
- BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
+ BuildMI(&BB, dl, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
// we create a PSEUDO_ALLOC (pseudo)instruction for now
/*
BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
// here we actually do the moving of args, and store them to the stack
// too if this is a varargs function:
for (int i = 0; i < count && i < 8; ++i) {
- BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
+ BuildMI(&BB, dl, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
if(F.isVarArg()) {
// if this is a varargs function, we copy the input registers to the stack
int FI = MFI->CreateFixedObject(8, tempOffset);
tempOffset+=8; //XXX: is it safe to use r22 like this?
- BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
+ BuildMI(&BB, dl, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
// FIXME: we should use st8.spill here, one day
- BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
+ BuildMI(&BB, dl, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
}
}
// Finally, inform the code generator which regs we return values in.
// (see the ISD::RET: case in the instruction selector)
- switch (getValueType(F.getReturnType())) {
- default: assert(0 && "i have no idea where to return this type!");
+ switch (getValueType(F.getReturnType()).getSimpleVT()) {
+ default: llvm_unreachable("i have no idea where to return this type!");
case MVT::isVoid: break;
case MVT::i1:
case MVT::i8:
MF.getRegInfo().addLiveOut(IA64::F8);
break;
}
-
- return ArgValues;
}
-std::pair<SDOperand, SDOperand>
-IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
- bool RetSExt, bool RetZExt,
- bool isVarArg, unsigned CallingConv,
- bool isTailCall, SDOperand Callee,
- ArgListTy &Args, SelectionDAG &DAG) {
+std::pair<SDValue, SDValue>
+IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
+ bool RetSExt, bool RetZExt, bool isVarArg,
+ bool isInreg, unsigned NumFixedArgs,
+ unsigned CallingConv,
+ bool isTailCall, SDValue Callee,
+ ArgListTy &Args, SelectionDAG &DAG,
+ DebugLoc dl) {
MachineFunction &MF = DAG.getMachineFunction();
// "stack frame not 16-byte aligned!");
NumBytes = (NumBytes+15) & ~15;
- Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
- SDOperand StackPtr;
- std::vector<SDOperand> Stores;
- std::vector<SDOperand> Converts;
- std::vector<SDOperand> RegValuesToPass;
+ SDValue StackPtr;
+ std::vector<SDValue> Stores;
+ std::vector<SDValue> Converts;
+ std::vector<SDValue> RegValuesToPass;
unsigned ArgOffset = 16;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
- SDOperand Val = Args[i].Node;
- MVT::ValueType ObjectVT = Val.getValueType();
- SDOperand ValToStore(0, 0), ValToConvert(0, 0);
+ SDValue Val = Args[i].Node;
+ MVT ObjectVT = Val.getValueType();
+ SDValue ValToStore(0, 0), ValToConvert(0, 0);
unsigned ObjSize=8;
- switch (ObjectVT) {
- default: assert(0 && "unexpected argument type!");
+ switch (ObjectVT.getSimpleVT()) {
+ default: llvm_unreachable("unexpected argument type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
ExtendKind = ISD::SIGN_EXTEND;
else if (Args[i].isZExt)
ExtendKind = ISD::ZERO_EXTEND;
- Val = DAG.getNode(ExtendKind, MVT::i64, Val);
+ Val = DAG.getNode(ExtendKind, dl, MVT::i64, Val);
// XXX: fall through
}
case MVT::i64:
break;
case MVT::f32:
//promote to 64-bits
- Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
+ Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
// XXX: fall through
case MVT::f64:
if(RegValuesToPass.size() >= 8) {
break;
}
- if(ValToStore.Val) {
- if(!StackPtr.Val) {
+ if(ValToStore.getNode()) {
+ if(!StackPtr.getNode()) {
StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
}
- SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
- Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
+ SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+ PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, PtrOff);
+ Stores.push_back(DAG.getStore(Chain, dl, ValToStore, PtrOff, NULL, 0));
ArgOffset += ObjSize;
}
- if(ValToConvert.Val) {
- Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
+ if(ValToConvert.getNode()) {
+ Converts.push_back(DAG.getNode(IA64ISD::GETFD, dl,
+ MVT::i64, ValToConvert));
}
}
// Emit all stores, make sure they occur before any copies into physregs.
if (!Stores.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
+ Chain = DAG.getNode(ISD::TokenFactor, dl,
+ MVT::Other, &Stores[0],Stores.size());
static const unsigned IntArgRegs[] = {
IA64::out0, IA64::out1, IA64::out2, IA64::out3,
IA64::F12, IA64::F13, IA64::F14, IA64::F15
};
- SDOperand InFlag;
+ SDValue InFlag;
// save the current GP, SP and RP : FIXME: do we need to do all 3 always?
- SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
+ SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r1,
+ MVT::i64, InFlag);
Chain = GPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
- SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
+ SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r12,
+ MVT::i64, InFlag);
Chain = SPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
- SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
+ SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::rp,
+ MVT::i64, InFlag);
Chain = RPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
// flagged for now, but shouldn't have to be (TODO)
unsigned seenConverts = 0;
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
- if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
- Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++],
- InFlag);
+ if(RegValuesToPass[i].getValueType().isFloatingPoint()) {
+ Chain = DAG.getCopyToReg(Chain, dl, IntArgRegs[i],
+ Converts[seenConverts++], InFlag);
InFlag = Chain.getValue(1);
}
}
// next copy args into the usual places, these are flagged
unsigned usedFPArgs = 0;
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain,
- MVT::isInteger(RegValuesToPass[i].getValueType()) ?
+ Chain = DAG.getCopyToReg(Chain, dl,
+ RegValuesToPass[i].getValueType().isInteger() ?
IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
InFlag = Chain.getValue(1);
}
}
*/
- std::vector<MVT::ValueType> NodeTys;
- std::vector<SDOperand> CallOperands;
+ std::vector<MVT> NodeTys;
+ std::vector<SDValue> CallOperands;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
CallOperands.push_back(Chain);
CallOperands.push_back(Callee);
// emit the call itself
- if (InFlag.Val)
+ if (InFlag.getNode())
CallOperands.push_back(InFlag);
else
- assert(0 && "this should never happen!\n");
+ llvm_unreachable("this should never happen!");
// to make way for a hack:
- Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys,
+ Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
&CallOperands[0], CallOperands.size());
InFlag = Chain.getValue(1);
// restore the GP, SP and RP after the call
- Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, IA64::r1, GPBeforeCall, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, IA64::r12, SPBeforeCall, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, IA64::rp, RPBeforeCall, InFlag);
InFlag = Chain.getValue(1);
- std::vector<MVT::ValueType> RetVals;
+ std::vector<MVT> RetVals;
RetVals.push_back(MVT::Other);
RetVals.push_back(MVT::Flag);
- MVT::ValueType RetTyVT = getValueType(RetTy);
- SDOperand RetVal;
+ MVT RetTyVT = getValueType(RetTy);
+ SDValue RetVal;
if (RetTyVT != MVT::isVoid) {
- switch (RetTyVT) {
- default: assert(0 && "Unknown value type to return!");
+ switch (RetTyVT.getSimpleVT()) {
+ default: llvm_unreachable("Unknown value type to return!");
case MVT::i1: { // bools are just like other integers (returned in r8)
// we *could* fall through to the truncate below, but this saves a
// few redundant predicate ops
- SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
+ SDValue boolInR8 = DAG.getCopyFromReg(Chain, dl, IA64::r8,
+ MVT::i64,InFlag);
InFlag = boolInR8.getValue(2);
Chain = boolInR8.getValue(1);
- SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
+ SDValue zeroReg = DAG.getCopyFromReg(Chain, dl, IA64::r0,
+ MVT::i64, InFlag);
InFlag = zeroReg.getValue(2);
Chain = zeroReg.getValue(1);
- RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
+ RetVal = DAG.getSetCC(dl, MVT::i1, boolInR8, zeroReg, ISD::SETNE);
break;
}
case MVT::i8:
case MVT::i16:
case MVT::i32:
- RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
+ RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
Chain = RetVal.getValue(1);
// keep track of whether it is sign or zero extended (todo: bools?)
/* XXX
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
- MVT::i64, RetVal, DAG.getValueType(RetTyVT));
+ dl, MVT::i64, RetVal, DAG.getValueType(RetTyVT));
*/
- RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
+ RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
break;
case MVT::i64:
- RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
+ RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
Chain = RetVal.getValue(1);
InFlag = RetVal.getValue(2); // XXX dead
break;
case MVT::f32:
- RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
+ RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
- RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
+ RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal,
+ DAG.getIntPtrConstant(0));
break;
case MVT::f64:
- RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
+ RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
InFlag = RetVal.getValue(2); // XXX dead
break;
}
}
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(NumBytes, getPointerTy()),
- DAG.getConstant(0, getPointerTy()),
- SDOperand());
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(0, true), SDValue());
return std::make_pair(RetVal, Chain);
}
-SDOperand IA64TargetLowering::
-LowerOperation(SDOperand Op, SelectionDAG &DAG) {
+SDValue IA64TargetLowering::
+LowerOperation(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
- default: assert(0 && "Should not custom lower this!");
+ default: llvm_unreachable("Should not custom lower this!");
case ISD::GlobalTLSAddress:
- assert(0 && "TLS not implemented for IA64.");
+ llvm_unreachable("TLS not implemented for IA64.");
case ISD::RET: {
- SDOperand AR_PFSVal, Copy;
+ SDValue AR_PFSVal, Copy;
switch(Op.getNumOperands()) {
default:
- assert(0 && "Do not know how to return this many arguments!");
- abort();
+ llvm_unreachable("Do not know how to return this many arguments!");
case 1:
- AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
- AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
+ AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
+ AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS,
AR_PFSVal);
- return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
+ return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal);
case 3: {
// Copy the result into the output register & restore ar.pfs
- MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
- unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
-
- AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
- Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
- SDOperand());
- AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
- Copy.getValue(1));
- return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other,
+ MVT ArgVT = Op.getOperand(1).getValueType();
+ unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8;
+
+ AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
+ Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, ArgReg,
+ Op.getOperand(1), SDValue());
+ AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), dl,
+ IA64::AR_PFS, AR_PFSVal, Copy.getValue(1));
+ return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other,
AR_PFSVal, AR_PFSVal.getValue(1));
}
}
- return SDOperand();
+ return SDValue();
}
case ISD::VAARG: {
- MVT::ValueType VT = getPointerTy();
+ MVT VT = getPointerTy();
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
+ SDValue VAList = DAG.getLoad(VT, dl, Op.getOperand(0), Op.getOperand(1),
SV, 0);
// Increment the pointer, VAList, to the next vaarg
- SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
- DAG.getConstant(MVT::getSizeInBits(VT)/8,
+ SDValue VAIncr = DAG.getNode(ISD::ADD, dl, VT, VAList,
+ DAG.getConstant(VT.getSizeInBits()/8,
VT));
// Store the incremented VAList to the legalized pointer
- VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
+ VAIncr = DAG.getStore(VAList.getValue(1), dl, VAIncr,
Op.getOperand(1), SV, 0);
// Load the actual argument out of the pointer VAList
- return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
+ return DAG.getLoad(Op.getValueType(), dl, VAIncr, VAList, NULL, 0);
}
case ISD::VASTART: {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
+ SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
+ return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
}
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
}
- return SDOperand();
+ return SDValue();
}
projects / oota-llvm.git / blobdiff