Fix cmake build, add TargetMachineRegistry.cpp that got restored in r75807

[oota-llvm.git] / lib / Target / IA64 / IA64InstrInfo.td

diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index 0fa63ff124c5138dccf8d3cf28c87f6e6e3289b9..2ab9897bddeb5630eebf8e3950d7ea3d8d6a0461 100644 (file)
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -21,8 +21,7 @@ include "IA64InstrFormats.td"
 
 def IA64getfd : SDNode<"IA64ISD::GETFD", SDTFPToIntOp, []>;
 
-def SDT_IA64RetFlag : SDTypeProfile<0, 0, []>;
-def retflag         : SDNode<"IA64ISD::RET_FLAG", SDT_IA64RetFlag,
+def retflag         : SDNode<"IA64ISD::RET_FLAG", SDTNone,
                            [SDNPHasChain, SDNPOptInFlag]>;
 
 //===---------
@@ -67,7 +66,7 @@ let PrintMethod = "printCallOperand" in
 def is32ones : PatLeaf<(i64 imm), [{
   // is32ones predicate - True if the immediate is 0x00000000FFFFFFFF 
   // Used to create ZXT4s appropriately 
-  uint64_t v = (uint64_t)N->getValue();
+  uint64_t v = (uint64_t)N->getZExtValue();
   return (v == 0x00000000FFFFFFFFLL);
 }]>;
 
@@ -76,36 +75,36 @@ def is32ones : PatLeaf<(i64 imm), [{
 // etc, through 0x00000000FFFFFFFF
 // Used to test for the suitability of mix* 
 def isMIX1Lable: PatLeaf<(i64 imm), [{
-  return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
+  return((uint64_t)N->getZExtValue()==0xFF00FF00FF00FF00LL);
 }]>;
 def isMIX1Rable: PatLeaf<(i64 imm), [{
-  return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
+  return((uint64_t)N->getZExtValue()==0x00FF00FF00FF00FFLL);
 }]>;
 def isMIX2Lable: PatLeaf<(i64 imm), [{
-  return((uint64_t)N->getValue()==0xFFFF0000FFFF0000LL);
+  return((uint64_t)N->getZExtValue()==0xFFFF0000FFFF0000LL);
 }]>;
 def isMIX2Rable: PatLeaf<(i64 imm), [{
-  return((uint64_t)N->getValue()==0x0000FFFF0000FFFFLL);
+  return((uint64_t)N->getZExtValue()==0x0000FFFF0000FFFFLL);
 }]>;
 def isMIX4Lable: PatLeaf<(i64 imm), [{
-  return((uint64_t)N->getValue()==0xFFFFFFFF00000000LL);
+  return((uint64_t)N->getZExtValue()==0xFFFFFFFF00000000LL);
 }]>;
 def isMIX4Rable: PatLeaf<(i64 imm), [{
-  return((uint64_t)N->getValue()==0x00000000FFFFFFFFLL);
+  return((uint64_t)N->getZExtValue()==0x00000000FFFFFFFFLL);
 }]>;
 
 def isSHLADDimm: PatLeaf<(i64 imm), [{
   // isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
   // - 0 is *not* okay.
   // Used to create shladd instructions appropriately
-  int64_t v = (int64_t)N->getValue();
+  int64_t v = (int64_t)N->getZExtValue();
   return (v >= 1 && v <= 4);
 }]>;
 
 def immSExt14  : PatLeaf<(i64 imm), [{
   // immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
   // field.  Used by instructions like 'adds'.
-  int64_t v = (int64_t)N->getValue();
+  int64_t v = (int64_t)N->getZExtValue();
   return (v <= 8191 && v >= -8192);
 }]>;
 
@@ -457,17 +456,6 @@ def : Pat<(i1  0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
 // tablegen support
 
-let isImplicitDef = 1 in {
-def IDEF : PseudoInstIA64<(outs variable_ops), (ins), "// IDEF">;
-
-def IDEF_GR_D : PseudoInstIA64_DAG<(outs GR:$reg), (ins), "// $reg = IDEF",
-    [(set GR:$reg, (undef))]>;
-def IDEF_FP_D : PseudoInstIA64_DAG<(outs FP:$reg), (ins), "// $reg = IDEF",
-    [(set FP:$reg, (undef))]>;
-def IDEF_PR_D : PseudoInstIA64_DAG<(outs PR:$reg), (ins), "// $reg = IDEF",
-    [(set PR:$reg, (undef))]>;
-}
-
 def IUSE : PseudoInstIA64<(outs), (ins variable_ops), "// IUSE">;
 def ADJUSTCALLSTACKUP : PseudoInstIA64<(outs), (ins variable_ops),
                                         "// ADJUSTCALLSTACKUP">;
@@ -558,7 +546,7 @@ let mayStore = 1 in {
     "stf.spill [$dstPtr] = $value">, isM;
 }
 
-let isSimpleLoad = 1 in {
+let canFoldAsLoad = 1 in {
   def LD1 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
     "ld1 $dst = [$srcPtr]">, isM;
   def LD2 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),