//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Duraid Madina and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the IA64 implementation of the MRegisterInfo class. This
-// file is responsible for the frame pointer elimination optimization on IA64.
+// This file contains the IA64 implementation of the TargetRegisterInfo class.
+// This file is responsible for the frame pointer elimination optimization
+// on IA64.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Support/CommandLine.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include <iostream>
using namespace llvm;
+IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
+ : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
+ TII(tii) {}
-IA64RegisterInfo::IA64RegisterInfo()
- : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP) {}
-
-void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, int FrameIdx,
- const TargetRegisterClass *RC) const{
-
- if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
- } else if (RC == IA64::GRRegisterClass) {
- BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
- }
- else if (RC == IA64::PRRegisterClass) {
- /* we use IA64::r2 as a temporary register for doing this hackery. */
- // first we load 0:
- BuildMI(MBB, MI, IA64::MOV, 1, IA64::r2).addReg(IA64::r0);
- // then conditionally add 1:
- BuildMI(MBB, MI, IA64::CADDIMM22, 3, IA64::r2).addReg(IA64::r2)
- .addImm(1).addReg(SrcReg);
- // and then store it to the stack
- BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(IA64::r2);
- } else assert(0 &&
- "sorry, I don't know how to store this sort of reg in the stack\n");
+const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
+ const {
+ static const unsigned CalleeSavedRegs[] = {
+ IA64::r5, 0
+ };
+ return CalleeSavedRegs;
}
-void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC)const{
-
- if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
- } else if (RC == IA64::GRRegisterClass) {
- BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
- } else if (RC == IA64::PRRegisterClass) {
- // first we load a byte from the stack into r2, our 'predicate hackery'
- // scratch reg
- BuildMI(MBB, MI, IA64::LD8, 1, IA64::r2).addFrameIndex(FrameIdx);
- // then we compare it to zero. If it _is_ zero, compare-not-equal to
- // r0 gives us 0, which is what we want, so that's nice.
- BuildMI(MBB, MI, IA64::CMPNE, 2, DestReg).addReg(IA64::r2).addReg(IA64::r0);
- } else assert(0 &&
- "sorry, I don't know how to load this sort of reg from the stack\n");
+const TargetRegisterClass* const*
+IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
+ &IA64::GRRegClass, 0
+ };
+ return CalleeSavedRegClasses;
}
-void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const {
-
- if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
- // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
- BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
- else // otherwise, MOV works (for both gen. regs and FP regs)
- BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
+BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ BitVector Reserved(getNumRegs());
+ Reserved.set(IA64::r0);
+ Reserved.set(IA64::r1);
+ Reserved.set(IA64::r2);
+ Reserved.set(IA64::r5);
+ Reserved.set(IA64::r12);
+ Reserved.set(IA64::r13);
+ Reserved.set(IA64::r22);
+ Reserved.set(IA64::rp);
+ return Reserved;
}
//===----------------------------------------------------------------------===//
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
//
-static bool hasFP(MachineFunction &MF) {
- return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
+bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ return NoFramePointerElim || MFI->hasVarSizedObjects();
}
void IA64RegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
-
if (hasFP(MF)) {
// If we have a frame pointer, turn the adjcallstackup instruction into a
// 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
// <amt>'
MachineInstr *Old = I;
- unsigned Amount = Old->getOperand(0).getImmedValue();
+ unsigned Amount = Old->getOperand(0).getImm();
+ DebugLoc dl = Old->getDebugLoc();
if (Amount != 0) {
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
Amount = (Amount+Align-1)/Align*Align;
- MachineInstr *New;
+ // Replace the pseudo instruction with a new instruction...
if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
- New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
- .addSImm(-Amount);
+ BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12)
+ .addReg(IA64::r12).addImm(-Amount);
} else {
assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
- New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
- .addSImm(Amount);
+ BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12)
+ .addReg(IA64::r12).addImm(Amount);
}
-
- // Replace the pseudo instruction with a new instruction...
- MBB.insert(I, New);
}
}
MBB.erase(I);
}
-void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
+void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, RegScavenger *RS)const{
+ assert(SPAdj == 0 && "Unexpected");
+
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
+ DebugLoc dl = MI.getDebugLoc();
bool FP = hasFP(MF);
- while (!MI.getOperand(i).isFrameIndex()) {
+ while (!MI.getOperand(i).isFI()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
- int FrameIndex = MI.getOperand(i).getFrameIndex();
+ int FrameIndex = MI.getOperand(i).getIndex();
// choose a base register: ( hasFP? framepointer : stack pointer )
unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
// Add the base register
- MI.SetMachineOperandReg(i, BaseRegister);
+ MI.getOperand(i).ChangeToRegister(BaseRegister, false);
// Now add the frame object offset to the offset from r1.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
Offset += MF.getFrameInfo()->getStackSize();
// XXX: we use 'r22' as another hack+slash temporary register here :(
- if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
- //fix up the old:
- MI.SetMachineOperandReg(i, IA64::r22);
- MI.getOperand(i).setUse(); // mark r22 as being used
- // (the bundler wants to know this)
+ if (Offset <= 8191 && Offset >= -8192) { // smallish offset
+ // Fix up the old:
+ MI.getOperand(i).ChangeToRegister(IA64::r22, false);
//insert the new
- MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
- .addReg(BaseRegister).addSImm(Offset);
- MBB.insert(II, nMI);
+ BuildMI(MBB, II, dl, TII.get(IA64::ADDIMM22), IA64::r22)
+ .addReg(BaseRegister).addImm(Offset);
} else { // it's big
//fix up the old:
- MI.SetMachineOperandReg(i, IA64::r22);
- MI.getOperand(i).setUse(); // mark r22 as being used
- // (the bundler wants to know this)
- MachineInstr* nMI;
- nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
- MBB.insert(II, nMI);
- nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
+ MI.getOperand(i).ChangeToRegister(IA64::r22, false);
+ BuildMI(MBB, II, dl, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
+ BuildMI(MBB, II, dl, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
.addReg(IA64::r22);
- MBB.insert(II, nMI);
}
}
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
- MachineInstr *MI;
bool FP = hasFP(MF);
+ DebugLoc dl = (MBBI != MBB.end() ?
+ MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
// first, we handle the 'alloc' instruction, that should be right up the
// top of any function
IA64::r126, IA64::r127 };
unsigned numStackedGPRsUsed=0;
- for(int i=0; i<96; i++) {
- if(MF.isPhysRegUsed(RegsInOrder[i]))
+ for (int i=0; i != 96; i++) {
+ if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i]))
numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
}
unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
- // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB)
+ // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
+ // a pseudo_alloc in the MBB)
unsigned dstRegOfPseudoAlloc;
for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
assert(MBBI != MBB.end());
}
}
- MI=BuildMI(IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0).\
+ if (MBBI != MBB.end()) dl = MBBI->getDebugLoc();
+
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ALLOC)).
+ addReg(dstRegOfPseudoAlloc).addImm(0).
addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
- MBB.insert(MBBI, MI);
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI->getStackSize();
- if (MFI->hasCalls() && !FP) {
- // We reserve argument space for call sites in the function immediately on
- // entry to the current function. This eliminates the need for add/sub
- // brackets around call sites.
- NumBytes += MFI->getMaxCallFrameSize();
- }
-
if(FP)
NumBytes += 8; // reserve space for the old FP
// adjust stack pointer: r12 -= numbytes
if (NumBytes <= 8191) {
- MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
- MBB.insert(MBBI, MI);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
+ addImm(-NumBytes);
} else { // we use r22 as a scratch register here
- MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes);
+ // first load the decrement into r22
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22).
+ addImm(-NumBytes);
// FIXME: MOVLSI32 expects a _u_32imm
- MBB.insert(MBBI, MI); // first load the decrement into r22
- MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
- MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
+ // then add (subtract) it to r12 (stack ptr)
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12)
+ .addReg(IA64::r12).addReg(IA64::r22);
+
}
// now if we need to, save the old FP and set the new
if (FP) {
- MI = BuildMI(IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5);
- MBB.insert(MBBI, MI);
+ BuildMI(MBB, MBBI,dl,TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
// this must be the last instr in the prolog ? (XXX: why??)
- MI = BuildMI(IA64::MOV, 1, IA64::r5).addReg(IA64::r12);
- MBB.insert(MBBI, MI);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
}
}
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
- MachineInstr *MI;
assert(MBBI->getOpcode() == IA64::RET &&
"Can only insert epilog into returning blocks");
-
+ DebugLoc dl = MBBI->getDebugLoc();
bool FP = hasFP(MF);
// Get the number of bytes allocated from the FrameInfo...
unsigned NumBytes = MFI->getStackSize();
//now if we need to, restore the old FP
- if (FP)
- {
+ if (FP) {
//copy the FP into the SP (discards allocas)
- MI=BuildMI(IA64::MOV, 1, IA64::r12).addReg(IA64::r5);
- MBB.insert(MBBI, MI);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
//restore the FP
- MI=BuildMI(IA64::LD8, 1, IA64::r5).addReg(IA64::r5);
- MBB.insert(MBBI, MI);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
}
- if (NumBytes != 0)
- {
+ if (NumBytes != 0) {
if (NumBytes <= 8191) {
- MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes);
- MBB.insert(MBBI, MI);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12).
+ addReg(IA64::r12).addImm(NumBytes);
} else {
- MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
- MBB.insert(MBBI, MI);
- MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
- MBB.insert(MBBI, MI);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22).
+ addImm(NumBytes);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
+ addReg(IA64::r22);
}
}
+}
+unsigned IA64RegisterInfo::getRARegister() const {
+ assert(0 && "What is the return address register");
+ return 0;
}
-void IA64RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
- MachineLocation &ML) const {
- assert(0 && "Needs to be defined for target");
- MachineFrameInfo *MFI = MF.getFrameInfo();
- bool FP = hasFP(MF);
-
- // FIXME - Needs to handle register variables.
- // FIXME - Faking that llvm number is same as gcc numbering.
- ML.set(getDwarfRegNum(FP ? IA64::r5 : IA64::r12),
- MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
+ return hasFP(MF) ? IA64::r5 : IA64::r12;
}
+unsigned IA64RegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned IA64RegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
+int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
+ assert(0 && "What is the dwarf register number");
+ return -1;
+}
#include "IA64GenRegisterInfo.inc"