Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile.

[oota-llvm.git] / lib / Target / MBlaze / TODO

diff --git a/lib/Target/MBlaze/TODO b/lib/Target/MBlaze/TODO
index cc0aa48288cf45090886c31f2e4e01c6973149c9..317d7c0a0b141e126277080b14be2a87d10f2b8f 100644 (file)
--- a/lib/Target/MBlaze/TODO
+++ b/lib/Target/MBlaze/TODO
@@ -1,32 +1,14 @@
 * Writing out ELF files is close to working but the following needs to
   be examined more closely:
-    - ELF relocation records are incorrect because the function
-      ELFObjectWriter::RecordRelocation is hard coded for X86/X86-64.
     - Relocations use 2-byte / 4-byte to terminology in reference to
       the size of the immediate value being changed. The Xilinx
       terminology seems to be (???) 4-byte / 8-byte in reference
       to the number of bytes of instructions that are being changed.
-    - BRLID and like instructions are always assumed to use a 4-byte
-      immediate value for the relocation and BEQID and like instructions
-      are always assumed to use a 2-byte immediate value for the relocation.
-      I think this means that conditional branches like BEQID can only
-      branch += 32768 bytes (~8192 instructions). We should allow conditional
-      branches to use 4-byte relocations but I'm not sure how to do that
-      right now.
-    - Relocation records for indirect calls are not being generated
-      correctly. These should emit and IMM 0 directly before the ORI
-      instruction that loads the register (just like when a BRLID
-      instruction is used instead of an ORI).
 
 * Code generation seems to work relatively well now but the following
   needs to be examined more closely:
     - The stack layout needs to be examined to make sure it meets
       the standard, especially in regards to var arg functions.
-    - The delay slot filler is ad hoc but seems to work. Load and
-      store instructions were prevented from being moved to delay
-      slots but I'm not sure that is necessary.
-    - The processor itineraries are copied from a different backend
-      and need to be updated to model the MicroBlaze correctly.
     - Look at the MBlazeGenFastISel.inc stuff and make use of it
       if appropriate.
 
@@ -34,9 +16,6 @@
   There are a few things that need to be looked at:
     - There are some instructions that are not generated by the backend
       and have not been tested as far as the parser is concerned.
-    - The assembly parser does not use any MicroBlaze specific directives.
+    - The assembly parser does not use many MicroBlaze specific directives.
       I should investigate if there are MicroBlaze specific directive and,
       if there are, add them.
-    - The instruction MFS and MTS use special names for some of the
-      special registers that can be accessed. These special register
-      names should be parsed by the assembly parser.