Prune some includes and forward declarations.

[oota-llvm.git] / lib / Target / Mips / MCTargetDesc / MipsMCCodeEmitter.cpp

diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 1115fec8aab563311005a53a31a232365c0887d5..9ebb6d25690d2d8071da1e240c72f0ee6731f722 100644 (file)
--- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -1,4 +1,4 @@
-//===-- MipsMCCodeEmitter.cpp - Convert Mips code to machine code ---------===//
+//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -34,10 +34,12 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
   const MCInstrInfo &MCII;
   const MCSubtargetInfo &STI;
   MCContext &Ctx;
+  bool IsLittleEndian;
 
 public:
   MipsMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
-                    MCContext &ctx) : MCII(mcii), STI(sti) , Ctx(ctx) {}
+                    MCContext &ctx, bool IsLittle) :
+            MCII(mcii), STI(sti) , Ctx(ctx), IsLittleEndian(IsLittle) {}
 
   ~MipsMCCodeEmitter() {}
 
@@ -47,9 +49,9 @@ public:
 
   void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
     // Output the instruction encoding in little endian byte order.
-    for (unsigned i = 0; i != Size; ++i) {
-      EmitByte(Val & 255, OS);
-      Val >>= 8;
+    for (unsigned i = 0; i < Size; ++i) {
+      unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
+      EmitByte((Val >> Shift) & 0xff, OS);
     }
   }
 
@@ -58,7 +60,7 @@ public:
 
   // getBinaryCodeForInstr - TableGen'erated function for getting the
   // binary encoding for an instruction.
-  unsigned getBinaryCodeForInstr(const MCInst &MI,
+  uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups) const;
 
   // getBranchJumpOpValue - Return binary encoding of the jump
@@ -88,11 +90,18 @@ public:
 }; // class MipsMCCodeEmitter
 }  // namespace
 
-MCCodeEmitter *llvm::createMipsMCCodeEmitter(const MCInstrInfo &MCII,
-                                             const MCSubtargetInfo &STI,
-                                             MCContext &Ctx)
+MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
+                                               const MCSubtargetInfo &STI,
+                                               MCContext &Ctx)
 {
-  return new MipsMCCodeEmitter(MCII, STI, Ctx);
+  return new MipsMCCodeEmitter(MCII, STI, Ctx, false);
+}
+
+MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
+                                               const MCSubtargetInfo &STI,
+                                               MCContext &Ctx)
+{
+  return new MipsMCCodeEmitter(MCII, STI, Ctx, true);
 }
 
 /// EncodeInstruction - Emit the instruction.
@@ -173,19 +182,33 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
   } else if (MO.isExpr()) {
     const MCExpr *Expr = MO.getExpr();
     MCExpr::ExprKind Kind = Expr->getKind();
+    unsigned Ret = 0;
+
+    if (Kind == MCExpr::Binary) {
+      const MCBinaryExpr *BE = static_cast<const MCBinaryExpr*>(Expr);
+      Expr = BE->getLHS();
+      Kind = Expr->getKind();
+      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(BE->getRHS());
+      assert((Kind == MCExpr::SymbolRef) && CE &&
+             "Binary expression must be sym+const.");
+      Ret = CE->getValue();
+    }
+
     if (Kind == MCExpr::SymbolRef) {
-      Mips::Fixups FixupKind = Mips::fixup_Mips_NONE;
-      MCSymbolRefExpr::VariantKind SymRefKind =
-          cast<MCSymbolRefExpr>(Expr)->getKind();
-      switch(SymRefKind) {
+      Mips::Fixups FixupKind;
+
+      switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
       case MCSymbolRefExpr::VK_Mips_GPREL:
         FixupKind = Mips::fixup_Mips_GPREL16;
         break;
       case MCSymbolRefExpr::VK_Mips_GOT_CALL:
         FixupKind = Mips::fixup_Mips_CALL16;
         break;
+      case MCSymbolRefExpr::VK_Mips_GOT16:
+        FixupKind = Mips::fixup_Mips_GOT_Global;
+        break;
       case MCSymbolRefExpr::VK_Mips_GOT:
-        FixupKind = Mips::fixup_Mips_GOT16;
+        FixupKind = Mips::fixup_Mips_GOT_Local;
         break;
       case MCSymbolRefExpr::VK_Mips_ABS_HI:
         FixupKind = Mips::fixup_Mips_HI16;
@@ -196,6 +219,15 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
       case MCSymbolRefExpr::VK_Mips_TLSGD:
         FixupKind = Mips::fixup_Mips_TLSGD;
         break;
+      case MCSymbolRefExpr::VK_Mips_TLSLDM:
+        FixupKind = Mips::fixup_Mips_TLSLDM;
+        break;
+      case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
+        FixupKind = Mips::fixup_Mips_DTPREL_HI;
+        break;
+      case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
+        FixupKind = Mips::fixup_Mips_DTPREL_LO;
+        break;
       case MCSymbolRefExpr::VK_Mips_GOTTPREL:
         FixupKind = Mips::fixup_Mips_GOTTPREL;
         break;
@@ -206,16 +238,14 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
         FixupKind = Mips::fixup_Mips_TPREL_LO;
         break;
       default:
-        return 0;
+        return Ret;
       } // switch
       Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
     } // if SymbolRef
     // All of the information is in the fixup.
-    return 0;
+    return Ret;
   }
   llvm_unreachable("Unable to encode MCOperand!");
-  // Not reached
-  return 0;
 }
 
 /// getMemEncoding - Return binary encoding of memory related operand.
@@ -234,15 +264,22 @@ MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
 unsigned
 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
                                       SmallVectorImpl<MCFixup> &Fixups) const {
-  // FIXME: implement
-  return 0;
+  assert(MI.getOperand(OpNo).isImm());
+  unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
+  return SizeEncoding - 1;
 }
 
+// FIXME: should be called getMSBEncoding
+//
 unsigned
 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
                                       SmallVectorImpl<MCFixup> &Fixups) const {
-  // FIXME: implement
-  return 0;
+  assert(MI.getOperand(OpNo-1).isImm());
+  assert(MI.getOperand(OpNo).isImm());
+  unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
+  unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
+
+  return Position + Size - 1;
 }
 
 #include "MipsGenMCCodeEmitter.inc"