[mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl.

[oota-llvm.git] / lib / Target / Mips / Makefile

diff --git a/lib/Target/Mips/Makefile b/lib/Target/Mips/Makefile
index 6ebffc76e06968826cb5c0c59155c76d39a10ccc..bcf951e861b05e130ab1c204d238f48915c4cda2 100644 (file)
--- a/lib/Target/Mips/Makefile
+++ b/lib/Target/Mips/Makefile
@@ -1,21 +1,25 @@
 ##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
-# 
+#
 #                     The LLVM Compiler Infrastructure
 #
-# This file was developed by Bruno Cardoso Lopes and is distributed under the 
-# University of Illinois Open Source License. See LICENSE.TXT for details.
-# 
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
 ##===----------------------------------------------------------------------===##
+
 LEVEL = ../../..
-LIBRARYNAME = LLVMMips
+LIBRARYNAME = LLVMMipsCodeGen
 TARGET = Mips
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
-                                                               MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
-                                                               MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
-                                                               MipsGenDAGISel.inc MipsGenCallingConv.inc \
-                                                               MipsGenSubtarget.inc
+BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
+                MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
+                MipsGenDAGISel.inc MipsGenCallingConv.inc \
+                MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \
+                MipsGenDisassemblerTables.inc \
+                MipsGenMCPseudoLowering.inc MipsGenAsmMatcher.inc
+
+DIRS = InstPrinter Disassembler AsmParser TargetInfo MCTargetDesc
 
 include $(LEVEL)/Makefile.common