ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics...

[oota-llvm.git] / lib / Target / Mips / Mips.td

diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td
index 1199cc47ace7962ea13d0953a3bdf8b82c193260..79ae5d2425f4685a5912bad8ca063410fabeef0b 100644 (file)
--- a/lib/Target/Mips/Mips.td
+++ b/lib/Target/Mips/Mips.td
@@ -13,7 +13,7 @@
 // Target-independent interfaces
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
@@ -33,20 +33,32 @@ def MipsInstrInfo : InstrInfo {
 // Mips Subtarget features                                                    //
 //===----------------------------------------------------------------------===//
 
-def FeatureGP64Bit      : SubtargetFeature<"gp64", "IsGP64bit", "true",
+def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide.">;
-def FeatureFP64Bit      : SubtargetFeature<"fp64", "IsFP64bit", "true",
+def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
                                 "Support 64-bit FP registers.">;
-def FeatureSingleFloat  : SubtargetFeature<"single-float", "IsSingleFloat",
+def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
                                 "true", "Only supports single precision float">;
-def FeatureAllegrexVFPU : SubtargetFeature<"allegrex-vfpu", "HasAllegrexVFPU", 
-                                "true", "Enable Allegrex VFPU instructions.">;
-def FeatureMips2        : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
+def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
                                 "Mips2 ISA Support">;
-def FeatureO32          : SubtargetFeature<"o32", "MipsABI", "O32",
+def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
                                 "Enable o32 ABI">;
-def FeatureEABI         : SubtargetFeature<"eabi", "MipsABI", "EABI",
+def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
                                 "Enable eabi ABI">;
+def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU", 
+                                "true", "Enable vector FPU instructions.">;
+def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true", 
+                                "Enable 'signext in register' instructions.">;
+def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true", 
+                                "Enable 'conditional move' instructions.">;
+def FeatureMulDivAdd   : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
+                                "Enable 'multiply add/sub' instructions.">;
+def FeatureMinMax      : SubtargetFeature<"minmax", "HasMinMax", "true",
+                                "Enable 'min/max' instructions.">;
+def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
+                                "Enable 'byte/half swap' instructions.">;
+def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
+                                "Enable 'count leading bits' instructions.">;
 
 //===----------------------------------------------------------------------===//
 // Mips processors supported.
@@ -63,9 +75,11 @@ def : Proc<"mips2", [FeatureMips2]>;
 def : Proc<"r6000", [FeatureMips2]>;
 
 // Allegrex is a 32bit subset of r4000, both for interger and fp registers, 
-// but much more similar to Mips2 than Mips3. 
-def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureAllegrexVFPU,
-                        FeatureEABI]>;
+// but much more similar to Mips2 than Mips3. It also contains some of 
+// Mips32/Mips32r2 instructions and a custom vector fpu processor. 
+def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, 
+      FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
+      FeatureMinMax, FeatureSwap, FeatureBitCount]>;
 
 def Mips : Target {
   let InstructionSet = MipsInstrInfo;