// Transformation Function - get Imm - 32.
def Subtract32 : SDNodeXForm<imm, [{
- return getI32Imm((unsigned)N->getZExtValue() - 32);
+ return getImm(N, (unsigned)N->getZExtValue() - 32);
}]>;
+// shamt field must fit in 5 bits.
+def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
+
// imm32_63 predicate - True if imm is in range [32, 63].
-def imm32_63 : ImmLeaf<i64,
+def imm32_63 : ImmLeaf<i32,
[{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
Subtract32>;
-//===----------------------------------------------------------------------===//
-// Instructions specific format
-//===----------------------------------------------------------------------===//
+// Is a 32-bit int.
+def immSExt32 : ImmLeaf<i64, [{return isInt<32>(Imm);}]>;
-// Arithmetic 3 register operands
-class ArithR64<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
- InstrItinClass itin, bit isComm = 0>:
- FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
- !strconcat(instr_asm, "\t$dst, $b, $c"),
- [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], itin> {
- let isCommutable = isComm;
-}
+// Transformation Function - get the higher 16 bits.
+def HIGHER : SDNodeXForm<imm, [{
+ return getImm(N, (N->getZExtValue() >> 32) & 0xFFFF);
+}]>;
-// Arithmetic 2 register operands
-class ArithI64<bits<6> op, string instr_asm, SDNode OpNode,
- Operand Od, PatLeaf imm_type> :
- FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, Od:$c),
- !strconcat(instr_asm, "\t$dst, $b, $c"),
- [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, imm_type:$c))], IIAlu>;
-
-// Logical
-let isCommutable = 1 in
-class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>:
- FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
- !strconcat(instr_asm, "\t$dst, $b, $c"),
- [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu>;
-
-class LogicI64<bits<6> op, string instr_asm, SDNode OpNode>:
- FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, uimm16_64:$c),
- !strconcat(instr_asm, "\t$dst, $b, $c"),
- [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, immZExt16:$c))], IIAlu>;
-
-let isCommutable = 1 in
-class LogicNOR64<bits<6> op, bits<6> func, string instr_asm>:
- FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
- !strconcat(instr_asm, "\t$dst, $b, $c"),
- [(set CPU64Regs:$dst, (not (or CPU64Regs:$b, CPU64Regs:$c)))], IIAlu>;
+// Transformation Function - get the highest 16 bits.
+def HIGHEST : SDNodeXForm<imm, [{
+ return getImm(N, (N->getZExtValue() >> 48) & 0xFFFF);
+}]>;
+//===----------------------------------------------------------------------===//
+// Instructions specific format
+//===----------------------------------------------------------------------===//
// Shifts
-class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm,
- SDNode OpNode, PatFrag PF>:
- FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, shamt_64:$c),
- !strconcat(instr_asm, "\t$dst, $b, $c"),
- [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, (i64 PF:$c)))],
- IIAlu> {
- let rs = _rs;
-}
-
-class LogicR_shift_rotate_reg64<bits<6> func, bits<5> _shamt, string instr_asm,
- SDNode OpNode>:
- FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$c, CPU64Regs:$b),
- !strconcat(instr_asm, "\t$dst, $b, $c"),
- [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu> {
- let shamt = _shamt;
+// 64-bit shift instructions.
+class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
+ SDNode OpNode>:
+ shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt,
+ CPU64Regs>;
+
+class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
+ SDNode OpNode>:
+ shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt,
+ CPU64Regs>;
+
+// Jump and Link (Call)
+let isCall=1, hasDelaySlot=1,
+ // All calls clobber the non-callee saved registers...
+ Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
+ K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
+ class JumpLink64<bits<6> op, string instr_asm>:
+ FJ<op, (outs), (ins calltarget64:$target, variable_ops),
+ !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
+ IIBranch>;
+
+ class JumpLinkReg64<bits<6> op, bits<6> func, string instr_asm>:
+ FR<op, func, (outs), (ins CPU64Regs:$rs, variable_ops),
+ !strconcat(instr_asm, "\t$rs"),
+ [(MipsJmpLink CPU64Regs:$rs)], IIBranch> {
+ let rt = 0;
+ let rd = 31;
+ let shamt = 0;
+ }
+
+ class BranchLink64<string instr_asm>:
+ FI<0x1, (outs), (ins CPU64Regs:$rs, brtarget:$imm16, variable_ops),
+ !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
}
// Mul, Div
-let Defs = [HI64, LO64] in {
- let isCommutable = 1 in
- class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>:
- FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
- !strconcat(instr_asm, "\t$a, $b"), [], itin>;
-
- class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
- FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
- !strconcat(instr_asm, "\t$$zero, $a, $b"),
- [(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
+class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
+ Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
+class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
+ Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
+
+multiclass Atomic2Ops64<PatFrag Op, string Opstr> {
+ def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, Requires<[NotN64]>;
+ def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]>;
}
-// Move from Hi/Lo
-let shamt = 0 in {
-let rs = 0, rt = 0 in
-class MoveFromLOHI64<bits<6> func, string instr_asm>:
- FR<0x00, func, (outs CPU64Regs:$dst), (ins),
- !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
-
-let rt = 0, rd = 0 in
-class MoveToLOHI64<bits<6> func, string instr_asm>:
- FR<0x00, func, (outs), (ins CPU64Regs:$src),
- !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
+multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
+ def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, Requires<[NotN64]>;
+ def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>,
+ Requires<[IsN64]>;
}
-// Count Leading Ones/Zeros in Word
-class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
- FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
- !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
- Requires<[HasBitCount]> {
- let shamt = 0;
- let rt = rd;
+let usesCustomInserter = 1, Predicates = [HasMips64] in {
+ defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
+ defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
+ defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">;
+ defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">;
+ defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">;
+ defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">;
+ defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">;
+ defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">;
}
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate)
-def DADDiu : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
-def DANDi : LogicI64<0x0c, "andi", and>;
+def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
+ CPU64Regs>;
+def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
-def ORi64 : LogicI64<0x0d, "ori", or>;
-def XORi64 : LogicI64<0x0e, "xori", xor>;
+def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
+def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
+def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
/// Arithmetic Instructions (3-Operand, R-Type)
-def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
-def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu>;
+def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
+def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
-def AND64 : LogicR64<0x24, "and", and>;
-def OR64 : LogicR64<0x25, "or", or>;
-def XOR64 : LogicR64<0x26, "xor", xor>;
-def NOR64 : LogicNOR64<0x00, 0x27, "nor">;
+def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
+def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
+def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
+def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
/// Shift Instructions
-def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
-def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>;
-def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5>;
-def DSLL32 : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>;
-def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>;
-def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>;
-def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>;
-def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>;
-def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
+def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
+def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
+def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
+def DSLL32 : shift_rotate_imm64_32<0x3c, 0x00, "dsll32", shl>;
+def DSRL32 : shift_rotate_imm64_32<0x3e, 0x00, "dsrl32", srl>;
+def DSRA32 : shift_rotate_imm64_32<0x3f, 0x00, "dsra32", sra>;
+def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>;
+def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>;
+def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>;
// Rotate Instructions
let Predicates = [HasMips64r2] in {
- def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>;
- def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
- imm32_63>;
- def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
+ def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
+ def DROTR32 : shift_rotate_imm64_32<0x3e, 0x01, "drotr32", rotr>;
+ def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
}
/// Load and Store Instructions
defm ULD : LoadM64<0x37, "uld", load_u, 1>;
defm USD : StoreM64<0x3f, "usd", store_u, 1>;
+/// Load-linked, Store-conditional
+def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>;
+def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]>;
+def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>;
+def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>;
+
/// Jump and Branch Instructions
+def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>;
+def JAL64 : JumpLink64<0x03, "jal">;
+def JALR64 : JumpLinkReg64<0x00, 0x09, "jalr">;
def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
/// Multiply and Divide Instructions.
-def DMULT : Mul64<0x1c, "dmult", IIImul>;
-def DMULTu : Mul64<0x1d, "dmultu", IIImul>;
+def DMULT : Mult64<0x1c, "dmult", IIImul>;
+def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
-let Defs = [HI64] in
- def MTHI64 : MoveToLOHI64<0x11, "mthi">;
-let Defs = [LO64] in
- def MTLO64 : MoveToLOHI64<0x13, "mtlo">;
-
-let Uses = [HI64] in
- def MFHI64 : MoveFromLOHI64<0x10, "mfhi">;
-let Uses = [LO64] in
- def MFLO64 : MoveFromLOHI64<0x12, "mflo">;
+def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
+def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
+def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
+def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
/// Count Leading
-def DCLZ : CountLeading64<0x24, "dclz",
- [(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
-def DCLO : CountLeading64<0x25, "dclo",
- [(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
+def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
+def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
+
+def LEA_ADDiu64 : EffectiveAddress<"addiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
+
+let Uses = [SP_64] in
+def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
+ Requires<[IsN64]>;
+
+def DEXT : ExtBase<3, "dext", CPU64Regs>;
+def DINS : InsBase<7, "dins", CPU64Regs>;
+
+def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
+ "dsll32\t$rd, $rt, 0", [], IIAlu>;
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
def : Pat<(i64 immZExt16:$in),
(ORi64 ZERO_64, imm:$in)>;
-// zextloadi32_u
-def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
- Requires<[IsN64]>;
-def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
- Requires<[NotN64]>;
+// 32-bit immediates
+def : Pat<(i64 immSExt32:$imm),
+ (ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>;
+
+// Arbitrary immediates
+def : Pat<(i64 imm:$imm),
+ (ORi64 (DSLL (ORi64 (DSLL (ORi64 (LUi64 (HIGHEST imm:$imm)),
+ (HIGHER imm:$imm)), 16), (HI16 imm:$imm)), 16),
+ (LO16 imm:$imm))>;
+
+// extended loads
+let Predicates = [NotN64] in {
+ def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64 addr:$a), 0), 0)>;
+ def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>;
+}
+let Predicates = [IsN64] in {
+ def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64_P8 addr:$a), 0), 0)>;
+ def : Pat<(zextloadi32_u addr:$a),
+ (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>;
+}
// hi/lo relocs
-def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
+def : Pat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
+def : Pat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
+def : Pat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
+def : Pat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
+
+def : Pat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
+def : Pat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
+def : Pat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
+def : Pat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
+
+def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
+ (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
+def : Pat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
+ (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
+def : Pat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
+ (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
+def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
+ (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
+
+def : WrapperPICPat<tglobaladdr, DADDiu, GP_64>;
+def : WrapperPICPat<tconstpool, DADDiu, GP_64>;
+def : WrapperPICPat<texternalsym, DADDiu, GP_64>;
+def : WrapperPICPat<tblockaddress, DADDiu, GP_64>;
+def : WrapperPICPat<tjumptable, DADDiu, GP_64>;
defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
ZERO_64>;
defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
+
+// select MipsDynAlloc
+def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>;
+
+// truncate
+def : Pat<(i32 (trunc CPU64Regs:$src)),
+ (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
+
+// 32-to-64-bit extension
+def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>;
projects / oota-llvm.git / blobdiff