-//===-- DelaySlotFiller.cpp - Mips delay slot filler ---------------------===//
+//===-- DelaySlotFiller.cpp - Mips Delay Slot Filler ----------------------===//
//
// The LLVM Compiler Infrastructure
//
STATISTIC(FilledSlots, "Number of delay slots filled");
STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
- "are not NOP.");
+ " are not NOP.");
static cl::opt<bool> EnableDelaySlotFiller(
"enable-mips-delay-filler",
cl::desc("Fill the Mips delay slots useful instructions."),
cl::Hidden);
+// This option can be used to silence complaints by machine verifier passes.
+static cl::opt<bool> SkipDelaySlotFiller(
+ "skip-mips-delay-filler",
+ cl::init(false),
+ cl::desc("Skip MIPS' delay slot filling pass."),
+ cl::Hidden);
+
namespace {
struct Filler : public MachineFunctionPass {
+ typedef MachineBasicBlock::instr_iterator InstrIter;
+ typedef MachineBasicBlock::reverse_instr_iterator ReverseInstrIter;
TargetMachine &TM;
const TargetInstrInfo *TII;
+ InstrIter LastFiller;
static char ID;
Filler(TargetMachine &tm)
bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction(MachineFunction &F) {
+ if (SkipDelaySlotFiller)
+ return false;
+
bool Changed = false;
for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI)
}
bool isDelayFiller(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator candidate);
+ InstrIter candidate);
- void insertCallUses(MachineBasicBlock::iterator MI,
- SmallSet<unsigned, 32>& RegDefs,
- SmallSet<unsigned, 32>& RegUses);
+ void insertCallUses(InstrIter MI,
+ SmallSet<unsigned, 32> &RegDefs,
+ SmallSet<unsigned, 32> &RegUses);
- void insertDefsUses(MachineBasicBlock::iterator MI,
- SmallSet<unsigned, 32>& RegDefs,
- SmallSet<unsigned, 32>& RegUses);
+ void insertDefsUses(InstrIter MI,
+ SmallSet<unsigned, 32> &RegDefs,
+ SmallSet<unsigned, 32> &RegUses);
- bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
+ bool IsRegInSet(SmallSet<unsigned, 32> &RegSet,
unsigned Reg);
- bool delayHasHazard(MachineBasicBlock::iterator candidate,
+ bool delayHasHazard(InstrIter candidate,
bool &sawLoad, bool &sawStore,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses);
- MachineBasicBlock::iterator
- findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
+ bool
+ findDelayInstr(MachineBasicBlock &MBB, InstrIter slot,
+ InstrIter &Filler);
};
bool Filler::
runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
- if (I->getDesc().hasDelaySlot()) {
- MachineBasicBlock::iterator D = MBB.end();
- MachineBasicBlock::iterator J = I;
-
- if (EnableDelaySlotFiller)
- D = findDelayInstr(MBB, I);
+ LastFiller = MBB.instr_end();
+ for (InstrIter I = MBB.instr_begin(); I != MBB.instr_end(); ++I)
+ if (I->hasDelaySlot()) {
++FilledSlots;
Changed = true;
- if (D == MBB.end())
- BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(Mips::NOP));
- else
- MBB.splice(++J, &MBB, D);
+ InstrIter D;
+
+ if (EnableDelaySlotFiller && findDelayInstr(MBB, I, D)) {
+ MBB.splice(llvm::next(I), &MBB, D);
+ ++UsefulSlots;
+ } else
+ BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
+
+ // Record the filler instruction that filled the delay slot.
+ // The instruction after it will be visited in the next iteration.
+ LastFiller = ++I;
+
+ // Set InsideBundle bit so that the machine verifier doesn't expect this
+ // instruction to be a terminator.
+ LastFiller->setIsInsideBundle();
}
return Changed;
return new Filler(tm);
}
-MachineBasicBlock::iterator
-Filler::findDelayInstr(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator slot) {
+bool Filler::findDelayInstr(MachineBasicBlock &MBB,
+ InstrIter slot,
+ InstrIter &Filler) {
SmallSet<unsigned, 32> RegDefs;
SmallSet<unsigned, 32> RegUses;
- bool sawLoad = false;
- bool sawStore = false;
-
- MachineBasicBlock::iterator I = slot;
- // Call's delay filler can def some of call's uses.
- if (slot->getDesc().isCall())
- insertCallUses(slot, RegDefs, RegUses);
- else
- insertDefsUses(slot, RegDefs, RegUses);
+ insertDefsUses(slot, RegDefs, RegUses);
- bool done = false;
-
- while (!done) {
- done = (I == MBB.begin());
-
- if (!done)
- --I;
+ bool sawLoad = false;
+ bool sawStore = false;
+ for (ReverseInstrIter I(slot); I != MBB.instr_rend(); ++I) {
// skip debug value
if (I->isDebugValue())
continue;
+ // Convert to forward iterator.
+ InstrIter FI(llvm::next(I).base());
+
if (I->hasUnmodeledSideEffects()
|| I->isInlineAsm()
|| I->isLabel()
- || isDelayFiller(MBB, I)
- || I->getDesc().isPseudo()
+ || FI == LastFiller
+ || I->isPseudo()
//
// Should not allow:
// ERET, DERET or WAIT, PAUSE. Need to add these to instruction
)
break;
- if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
- insertDefsUses(I, RegDefs, RegUses);
+ if (delayHasHazard(FI, sawLoad, sawStore, RegDefs, RegUses)) {
+ insertDefsUses(FI, RegDefs, RegUses);
continue;
}
- return I;
+ Filler = FI;
+ return true;
}
- return MBB.end();
+
+ return false;
}
-bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
- bool &sawLoad,
- bool &sawStore,
+bool Filler::delayHasHazard(InstrIter candidate,
+ bool &sawLoad, bool &sawStore,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses) {
if (candidate->isImplicitDef() || candidate->isKill())
return true;
// Loads or stores cannot be moved past a store to the delay slot
- // and stores cannot be moved past a load.
- if (candidate->getDesc().mayLoad()) {
+ // and stores cannot be moved past a load.
+ if (candidate->mayLoad()) {
if (sawStore)
return true;
sawLoad = true;
}
- if (candidate->getDesc().mayStore()) {
+ if (candidate->mayStore()) {
if (sawStore)
return true;
sawStore = true;
return true;
}
+ assert((!candidate->isCall() && !candidate->isReturn()) &&
+ "Cannot put calls or returns in delay slot.");
+
for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
const MachineOperand &MO = candidate->getOperand(i);
- if (!MO.isReg())
- continue; // skip
+ unsigned Reg;
- unsigned Reg = MO.getReg();
+ if (!MO.isReg() || !(Reg = MO.getReg()))
+ continue; // skip
if (MO.isDef()) {
// check whether Reg is defined or used before delay slot.
return false;
}
-void Filler::insertCallUses(MachineBasicBlock::iterator MI,
- SmallSet<unsigned, 32>& RegDefs,
- SmallSet<unsigned, 32>& RegUses) {
- switch(MI->getOpcode()) {
- default: llvm_unreachable("Unknown opcode.");
- case Mips::JAL:
- RegDefs.insert(31);
- break;
- case Mips::JALR:
- assert(MI->getNumOperands() >= 1);
- const MachineOperand &Reg = MI->getOperand(0);
- assert(Reg.isReg() && "JALR first operand is not a register.");
- RegUses.insert(Reg.getReg());
- RegDefs.insert(31);
- break;
- }
-}
-
// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
-void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
- SmallSet<unsigned, 32>& RegDefs,
- SmallSet<unsigned, 32>& RegUses) {
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+void Filler::insertDefsUses(InstrIter MI,
+ SmallSet<unsigned, 32> &RegDefs,
+ SmallSet<unsigned, 32> &RegUses) {
+ // If MI is a call or return, just examine the explicit non-variadic operands.
+ MCInstrDesc MCID = MI->getDesc();
+ unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
+ MI->getNumOperands();
+
+ // Add RA to RegDefs to prevent users of RA from going into delay slot.
+ if (MI->isCall())
+ RegDefs.insert(Mips::RA);
+
+ for (unsigned i = 0; i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg())
- continue;
+ unsigned Reg;
- unsigned Reg = MO.getReg();
- if (Reg == 0)
+ if (!MO.isReg() || !(Reg = MO.getReg()))
continue;
+
if (MO.isDef())
RegDefs.insert(Reg);
- if (MO.isUse())
+ else if (MO.isUse())
RegUses.insert(Reg);
}
}
//returns true if the Reg or its alias is in the RegSet.
-bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) {
- if (RegSet.count(Reg))
- return true;
- // check Aliased Registers
- for (const unsigned *Alias = TM.getRegisterInfo()->getAliasSet(Reg);
- *Alias; ++Alias)
- if (RegSet.count(*Alias))
+bool Filler::IsRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) {
+ // Check Reg and all aliased Registers.
+ for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
+ AI.isValid(); ++AI)
+ if (RegSet.count(*AI))
return true;
-
return false;
}
-
-// return true if the candidate is a delay filler.
-bool Filler::isDelayFiller(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator candidate) {
- if (candidate == MBB.begin())
- return false;
- const MCInstrDesc &prevdesc = (--candidate)->getDesc();
- return prevdesc.hasDelaySlot();
-}
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