[FastISel][AArch64] Cleanup and simplify 'fastSelectInstruction'. NFC.

[oota-llvm.git] / lib / Target / Mips / MipsFastISel.cpp

diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp
index af4c4ab69e36eccbd6a6753bbe03b3999ac70618..9dde1d8e5e8f8a3ddf46c4e4571daa8cb8c2ab61 100644 (file)
--- a/lib/Target/Mips/MipsFastISel.cpp
+++ b/lib/Target/Mips/MipsFastISel.cpp
@@ -64,8 +64,8 @@ public:
                        (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
   }
 
-  bool TargetSelectInstruction(const Instruction *I) override;
-  unsigned TargetMaterializeConstant(const Constant *C) override;
+  bool fastSelectInstruction(const Instruction *I) override;
+  unsigned fastMaterializeConstant(const Constant *C) override;
 
   bool ComputeAddress(const Value *Obj, Address &Addr);
 
@@ -89,7 +89,7 @@ private:
   // for some reason, this default is not generated by tablegen
   // so we explicitly generate it here.
   //
-  unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
+  unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
     return 0;
@@ -110,7 +110,7 @@ private:
   }
 
   MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
-                                      unsigned MemReg, int64_t MemOffset) {
+                                   unsigned MemReg, int64_t MemOffset) {
     return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
   }
 
@@ -194,7 +194,7 @@ bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
 
 // Materialize a constant into a register, and return the register
 // number (or zero if we failed to handle it).
-unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) {
+unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
   EVT CEVT = TLI.getValueType(C->getType(), true);
 
   // Only handle simple types.
@@ -259,7 +259,7 @@ bool MipsFastISel::SelectLoad(const Instruction *I) {
   unsigned ResultReg;
   if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
     return false;
-  UpdateValueMap(I, ResultReg);
+  updateValueMap(I, ResultReg);
   return true;
 }
 
@@ -303,7 +303,7 @@ bool MipsFastISel::SelectRet(const Instruction *I) {
   return true;
 }
 
-bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
+bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
   if (!TargetSupported)
     return false;
   switch (I->getOpcode()) {
@@ -353,15 +353,23 @@ unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
     return 0;
   EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
       GV, 0, MipsII::MO_GOT);
+  if ((GV->hasInternalLinkage() ||
+       (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
+    unsigned TempReg = createResultReg(RC);
+    EmitInst(Mips::ADDiu, TempReg).addReg(DestReg).addGlobalAddress(
+        GV, 0, MipsII::MO_ABS_LO);
+    DestReg = TempReg;
+  }
   return DestReg;
 }
+
 unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
     return 0;
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   const ConstantInt *CI = cast<ConstantInt>(C);
   int64_t Imm;
-  if (CI->isNegative())
+  if ((VT != MVT::i1) && CI->isNegative())
     Imm = CI->getSExtValue();
   else
     Imm = CI->getZExtValue();