// FP load.
class FPLoad<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
Operand MemOpnd>:
- FFI<op, (outs RC:$ft), (ins MemOpnd:$base),
- !strconcat(opstr, "\t$ft, $base"), [(set RC:$ft, (FOp addr:$base))]>;
+ FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
+ !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (FOp addr:$addr))],
+ IILoad>;
// FP store.
class FPStore<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
Operand MemOpnd>:
- FFI<op, (outs), (ins RC:$ft, MemOpnd:$base),
- !strconcat(opstr, "\t$ft, $base"), [(store RC:$ft, addr:$base)]>;
+ FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
+ !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
+ IIStore>;
// Instructions that convert an FP value to 32-bit fixed point.
multiclass FFR1_W_M<bits<6> funct, string opstr> {
// stores, and moves between floating-point and integer registers.
// When defining instructions, we reference all 32-bit registers,
// regardless of register aliasing.
-let fd = 0 in {
- /// Move Control Registers From/To CPU Registers
- def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
+
+class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
+ FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
+ bits<5> rt;
+ let ft = rt;
+ let fd = 0;
+}
+
+/// Move Control Registers From/To CPU Registers
+def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
"cfc1\t$rt, $fs", []>;
- def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
- "ctc1\t$fs, $rt", []>;
+def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
+ "ctc1\t$rt, $fs", []>;
- def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
+def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
"mfc1\t$rt, $fs",
[(set CPURegs:$rt, (bitconvert FGR32:$fs))]>;
- def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
+def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
"mtc1\t$rt, $fs",
[(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
-}
+
+def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs),
+ "dmfc1\t$rt, $fs",
+ [(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>;
+
+def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt),
+ "dmtc1\t$rt, $fs",
+ [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>;
def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
}
/// Floating-point Aritmetic
-defm FADD : FFR2P_M<0x10, "add", fadd, 1>;
+defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
defm FDIV : FFR2P_M<0x03, "div", fdiv>;
defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
defm FSUB : FFR2P_M<0x01, "sub", fsub>;
/// Floating Point Branch of False/True (Likely)
let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
- class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
- (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
- [(MipsFPBrcond op, bb:$dst)]>;
+ class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
+ FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
+ [(MipsFPBrcond op, bb:$dst)]> {
+ let Inst{20-18} = 0;
+ let Inst{17} = nd;
+ let Inst{16} = tf;
+}
-def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
-def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
+def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
+def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
//===----------------------------------------------------------------------===//
// Floating Point Flag Conditions
def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
+class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
+ FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc),
+ !strconcat("c.$cc.", typestr, "\t$fs, $ft"),
+ [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>;
+
/// Floating Point Compare
let Defs=[FCR31] in {
- def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
- "c.$cc.s\t$fs, $ft",
- [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
-
- def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
- "c.$cc.d\t$fs, $ft",
- [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>,
- Requires<[NotFP64bit]>;
+ def FCMP_S32 : FCMP<0x10, FGR32, "s">;
+ def FCMP_D32 : FCMP<0x11, AFGR64, "d">, Requires<[NotFP64bit]>;
+ def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]>;
}
//===----------------------------------------------------------------------===//
def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
-def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
-
def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
-def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
let Predicates = [NotFP64bit] in {
+ def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
+ def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
}
+let Predicates = [IsFP64bit] in {
+ def : Pat<(f64 fpimm0), (DMTC1 ZERO_64)>;
+ def : Pat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
+
+ def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D64_W (MTC1 CPURegs:$src))>;
+ def : Pat<(f32 (sint_to_fp CPU64Regs:$src)),
+ (CVT_S_L (DMTC1 CPU64Regs:$src))>;
+ def : Pat<(f64 (sint_to_fp CPU64Regs:$src)),
+ (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
+
+ def : Pat<(i32 (fp_to_sint FGR64:$src)), (MFC1 (TRUNC_W_D64 FGR64:$src))>;
+ def : Pat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
+ def : Pat<(i64 (fp_to_sint FGR64:$src)), (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
+
+ def : Pat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
+ def : Pat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
+}
\ No newline at end of file
projects / oota-llvm.git / blobdiff