-//===- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
+//===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
//
-// This file contains the Mips implementation of the TargetInstrInfo class.
+// This file describes the Mips FPU instruction set.
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Floating Point Instructions
// ------------------------
// * 64bit fp:
// * 32bit fp:
// - 16 even 32-bit registers - single and double (aliased)
// - 32 32-bit registers (within single-only mode)
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Floating Point Compare and Branch
def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
let PrintMethod = "printFCCOperand" in
def condcode : Operand<i32>;
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Feature predicates.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
-def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Instruction Class Templates
//
// A set of multiclasses is used to address the register usage.
// D64 - double precision in 32 64bit fp registers (In64BitMode)
//
// Only S32 and D32 are supported right now.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
multiclass FFR1_1<bits<6> funct, string asmstr>
{
def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
- !strconcat(asmstr, ".s $fd, $fs"), []>;
+ !strconcat(asmstr, ".s\t$fd, $fs"), []>;
def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs),
- !strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
+ !strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[In32BitMode]>;
}
multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
{
def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
- !strconcat(asmstr, ".s $fd, $fs"),
+ !strconcat(asmstr, ".s\t$fd, $fs"),
[(set FGR32:$fd, (FOp FGR32:$fs))]>;
def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
- !strconcat(asmstr, ".d $fd, $fs"),
- [(set AFGR64:$fd, (FOp AFGR64:$fs))]>,
- Requires<[In32BitMode]>;
+ !strconcat(asmstr, ".d\t$fd, $fs"),
+ [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
}
class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
RegisterClass RcDst, string asmstr>:
FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
- !strconcat(asmstr, " $fd, $fs"), []>;
+ !strconcat(asmstr, "\t$fd, $fs"), []>;
-multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
+multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp, bit isComm = 0> {
+ let isCommutable = isComm in {
def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
(ins FGR32:$fs, FGR32:$ft),
- !strconcat(asmstr, ".s $fd, $fs, $ft"),
+ !strconcat(asmstr, ".s\t$fd, $fs, $ft"),
[(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
(ins AFGR64:$fs, AFGR64:$ft),
- !strconcat(asmstr, ".d $fd, $fs, $ft"),
+ !strconcat(asmstr, ".d\t$fd, $fs, $ft"),
[(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
Requires<[In32BitMode]>;
+ }
}
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Floating Point Instructions
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
let ft = 0 in {
defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
let fd = 0 in {
/// Move Control Registers From/To CPU Registers
def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
- "cfc1 $rt, $fs", []>;
+ "cfc1\t$rt, $fs", []>;
def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
- "ctc1 $fs, $rt", []>;
+ "ctc1\t$fs, $rt", []>;
def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
- "mfc1 $rt, $fs", []>;
+ "mfc1\t$rt, $fs", []>;
def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
- "mtc1 $rt, $fs", []>;
+ "mtc1\t$rt, $fs", []>;
}
def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
- "mov.s $fd, $fs", []>;
+ "mov.s\t$fd, $fs", []>;
def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
- "mov.d $fd, $fs", []>;
+ "mov.d\t$fd, $fs", []>;
/// Floating Point Memory Instructions
-let Predicates = [IsNotSingleFloat, IsNotMipsI] in {
+let Predicates = [IsNotSingleFloat] in {
def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
- "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
+ "ldc1\t$ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
- "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
+ "sdc1\t$ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
}
// LWC1 and SWC1 can always be emitted with odd registers.
-def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
+def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1\t$ft, $addr",
[(set FGR32:$ft, (load addr:$addr))]>;
def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr),
- "swc1 $ft, $addr", [(store FGR32:$ft, addr:$addr)]>;
+ "swc1\t$ft, $addr", [(store FGR32:$ft, addr:$addr)]>;
/// Floating-point Aritmetic
-defm FADD : FFR1_4<0x10, "add", fadd>;
+defm FADD : FFR1_4<0x10, "add", fadd, 1>;
defm FDIV : FFR1_4<0x03, "div", fdiv>;
-defm FMUL : FFR1_4<0x02, "mul", fmul>;
+defm FMUL : FFR1_4<0x02, "mul", fmul, 1>;
defm FSUB : FFR1_4<0x01, "sub", fsub>;
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Floating Point Branch Codes
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
// They must be kept in synch.
def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
/// Floating Point Branch of False/True (Likely)
let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
- (ins brtarget:$dst), !strconcat(asmstr, " $dst"),
+ (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
[(MipsFPBrcond op, bb:$dst)]>;
def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Floating Point Flag Conditions
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
// They must be kept in synch.
def MIPS_FCOND_F : PatLeaf<(i32 0)>;
def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
/// Floating Point Compare
-let hasDelaySlot = 1, Defs=[FCR31] in {
+let Defs=[FCR31] in {
def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
- "c.$cc.s $fs, $ft",
+ "c.$cc.s\t$fs, $ft",
[(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
- "c.$cc.d $fs, $ft",
+ "c.$cc.d\t$fs, $ft",
[(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>,
Requires<[In32BitMode]>;
}
// Conditional moves:
-// These instructions are expanded in
+// These instructions are expanded in
// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
// conditional move instructions.
// flag:int, data:float
def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
}
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Floating Point Pseudo-Instructions
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
"# MOVCCRToCCR", []>;
[(set CPURegs:$dst,
(MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
// Floating Point Patterns
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
def fpimm0 : PatLeaf<(fpimm), [{
return N->isExactlyValue(+0.0);
}]>;
def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
+def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;
projects / oota-llvm.git / blobdiff