let mayStore = 1;
}
+class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
+ SDPatternOperator OpNode= null_frag> :
+ InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+ [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
+ let DecoderMethod = "DecodeFMem2";
+ let mayStore = 1;
+}
+
+class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
+ SDPatternOperator OpNode= null_frag> :
+ InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+ [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
+ let DecoderMethod = "DecodeFMem2";
+ let mayLoad = 1;
+}
+
+class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
+ SDPatternOperator OpNode= null_frag> :
+ InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+ [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
+ let DecoderMethod = "DecodeFMem3";
+ let mayStore = 1;
+}
+
+class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
+ SDPatternOperator OpNode= null_frag> :
+ InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+ [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
+ let DecoderMethod = "DecodeFMem3";
+ let mayLoad = 1;
+}
+
class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
}
class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
- SDPatternOperator Op = null_frag> :
+ SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
!strconcat(opstr, "\t$fcc, $offset"),
[(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
FrmFI, opstr> {
let isBranch = 1;
let isTerminator = 1;
- let hasDelaySlot = 1;
+ let hasDelaySlot = DelaySlot;
let Defs = [AT];
}
let isCodeGenOnly = 1;
}
-class C_COND_FT<string CondStr, string Typestr,
- RegisterOperand RC, InstrItinClass itin> :
- InstSE<(outs), (ins FCCRegsOpnd:$cc, RC:$fs, RC:$ft),
- !strconcat("c.", CondStr, ".", Typestr, "\t $cc, $fs, $ft"),
- [], itin, FrmFR>;
+class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
+ InstrItinClass itin> :
+ InstSE<(outs), (ins RC:$fs, RC:$ft),
+ !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin,
+ FrmFR>;
-multiclass C_COND_M<string TypeStr, RegisterOperand RC,
- bits<5> fmt, InstrItinClass itin> {
+multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
+ InstrItinClass itin> {
def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>;
def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>;
def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>;
def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>;
}
-
-defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>,
- INSN_MIPS4_32_NOT_32R6_64R6;
-defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>,
- INSN_MIPS4_32_NOT_32R6_64R6, AdditionalRequires<[NotFP64bit]>;
+defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
+defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
+ AdditionalRequires<[NotFP64bit]>;
let DecoderNamespace = "Mips64" in
-defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>,
- INSN_MIPS4_32_NOT_32R6_64R6, AdditionalRequires<[IsFP64bit]>;
-
-class CCInstAlias<string CondStr, string TypeStr, dag Result>:
- MipsInstAlias<!strconcat("c.", CondStr, ".", TypeStr, "\t $fs, $ft"),
- Result>, ISA_MIPS1_NOT_32R6_64R6;
-
-multiclass CCondInstAlias<string CondStr,
- Instruction CondS, Instruction CondD32,
- Instruction CondD64> {
- def : CCInstAlias<CondStr, "s",
- (CondS FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft )>;
- def : CCInstAlias<CondStr, "d" ,
- (CondD32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft )>,
- AdditionalRequires<[NotFP64bit]>;
- def : CCInstAlias<CondStr, "d",
- (CondD64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft )>,
- AdditionalRequires<[IsFP64bit]>;
-}
-
-defm : CCondInstAlias<"f", C_F_S, C_F_D32, C_F_D64>;
-defm : CCondInstAlias<"un", C_UN_S, C_UN_D32, C_UN_D64>;
-defm : CCondInstAlias<"eq", C_EQ_S, C_EQ_D32, C_EQ_D64>;
-defm : CCondInstAlias<"ueq", C_UEQ_S, C_UEQ_D32, C_UEQ_D64>;
-defm : CCondInstAlias<"olt", C_OLT_S, C_OLT_D32, C_OLT_D64>;
-defm : CCondInstAlias<"ult", C_ULT_S, C_ULT_D32, C_ULT_D64>;
-defm : CCondInstAlias<"ole", C_OLE_S, C_OLE_D32, C_OLE_D64>;
-defm : CCondInstAlias<"ule", C_ULE_S, C_ULE_D32, C_ULE_D64>;
-defm : CCondInstAlias<"sf", C_SF_S, C_SF_D32, C_SF_D64>;
-defm : CCondInstAlias<"ngle", C_NGLE_S, C_NGLE_D32, C_NGLE_D64>;
-defm : CCondInstAlias<"seq", C_SEQ_S, C_SEQ_D32, C_SEQ_D64>;
-defm : CCondInstAlias<"ngl", C_NGL_S, C_NGL_D32, C_NGL_D64>;
-defm : CCondInstAlias<"lt", C_LT_S, C_LT_D32, C_LT_D64>;
-defm : CCondInstAlias<"nge", C_NGE_S, C_NGE_D32, C_NGE_D64>;
-defm : CCondInstAlias<"le", C_LE_S, C_LE_D32, C_LE_D64>;
-defm : CCondInstAlias<"ngt", C_NGT_S, C_NGT_D32, C_NGT_D64>;
+defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
+ AdditionalRequires<[IsFP64bit]>;
//===----------------------------------------------------------------------===//
// Floating Point Instructions
// Cop2 Memory Instructions
// FIXME: These aren't really FPU instructions and as such don't belong in this
// file
-def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
+def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
ISA_MIPS1_NOT_32R6_64R6;
-def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
+def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
ISA_MIPS1_NOT_32R6_64R6;
-def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
+def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
ISA_MIPS2_NOT_32R6_64R6;
-def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
+def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
ISA_MIPS2_NOT_32R6_64R6;
// Cop3 Memory Instructions
// FIXME: These aren't really FPU instructions and as such don't belong in this
// file
let DecoderNamespace = "COP3_" in {
- def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
- def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
- def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
+ def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
+ def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
+ def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
ISA_MIPS2;
- def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
+ def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
ISA_MIPS2;
}
def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
+def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>,
+ BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
+def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>,
+ BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
//===----------------------------------------------------------------------===//
// Floating Point Flag Conditions
//===----------------------------------------------------------------------===//
def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
+ ISA_MIPS2_NOT_32R6_64R6;
def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
+ ISA_MIPS2_NOT_32R6_64R6;
//===----------------------------------------------------------------------===//
// Floating Point Patterns
projects / oota-llvm.git / blobdiff