def FrmFI : Format<5>;
def FrmOther : Format<6>; // Instruction w/ a custom format
+class MMRel;
+
+def Std2MicroMips : InstrMapping {
+ let FilterClass = "MMRel";
+ // Instructions with the same BaseOpcode and isNVStore values form a row.
+ let RowFields = ["BaseOpcode"];
+ // Instructions with the same predicate sense form a column.
+ let ColFields = ["Arch"];
+ // The key column is the unpredicated instructions.
+ let KeyCol = ["se"];
+ // Value columns are PredSense=true and PredSense=false
+ let ValueCols = [["se"], ["micromips"]];
+}
+
+class StdArch {
+ string Arch = "se";
+}
+
// Generic Mips Format
class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format f>: Instruction
// Mips32/64 Instruction Format
class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin, Format f>:
+ InstrItinClass itin, Format f, string opstr = ""> :
MipsInst<outs, ins, asmstr, pattern, itin, f> {
let Predicates = [HasStdEnc];
+ string BaseOpcode = opstr;
+ string Arch;
}
// Mips Pseudo Instructions Format
let Inst{2-0} = sel;
}
-class ADD_FM<bits<6> op, bits<6> funct> {
+class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
bits<5> rd;
bits<5> rs;
bits<5> rt;
let Inst{5-0} = funct;
}
-class ADDI_FM<bits<6> op> {
+class ADDI_FM<bits<6> op> : StdArch {
bits<5> rs;
bits<5> rt;
bits<16> imm16;
let Inst{15-0} = imm16;
}
-class SRA_FM<bits<6> funct, bit rotate> {
+class SRA_FM<bits<6> funct, bit rotate> : StdArch {
bits<5> rd;
bits<5> rt;
bits<5> shamt;
let Inst{5-0} = funct;
}
-class SRLV_FM<bits<6> funct, bit rotate> {
+class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
bits<5> rd;
bits<5> rt;
bits<5> rs;
let Inst{15-0} = offset;
}
-class SLTI_FM<bits<6> op> {
+class SLTI_FM<bits<6> op> : StdArch {
bits<5> rt;
bits<5> rs;
bits<16> imm16;
let Inst{15-0} = imm16;
}
-class NOP_FM {
- bits<32> Inst;
-
- let Inst{31-0} = 0;
-}
-
class JALR_FM {
+ bits<5> rd;
bits<5> rs;
bits<32> Inst;
let Inst{31-26} = 0;
let Inst{25-21} = rs;
let Inst{20-16} = 0;
- let Inst{15-11} = 31;
+ let Inst{15-11} = rd;
let Inst{10-6} = 0;
let Inst{5-0} = 9;
}
let Inst{5-0} = 0xf;
}
-class MULT_FM<bits<6> op, bits<6> funct> {
+class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
bits<5> rs;
bits<5> rt;
let Inst{5-0} = 0x3b;
}
+class TEQ_FM<bits<6> funct> {
+ bits<5> rs;
+ bits<5> rt;
+ bits<10> code_;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0;
+ let Inst{25-21} = rs;
+ let Inst{20-16} = rt;
+ let Inst{15-6} = code_;
+ let Inst{5-0} = funct;
+}
+
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS
let Inst{10-0} = 0;
}
-class LW_FM<bits<6> op> {
+class LW_FM<bits<6> op> : StdArch {
bits<5> rt;
bits<21> addr;