//
//===----------------------------------------------------------------------===//
-//#include "Mips.h"
#include "MipsInstrInfo.h"
#include "MipsTargetMachine.h"
+#include "MipsMachineFunction.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "MipsGenInstrInfo.inc"
using namespace llvm;
TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
static bool isZeroImm(const MachineOperand &op) {
- return op.isImmediate() && op.getImm() == 0;
+ return op.isImm() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
bool MipsInstrInfo::
-isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const
+isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SrcSubIdx, unsigned &DstSubIdx) const
{
- // addu $dst, $src, $zero || addu $dst, $zero, $src
- // or $dst, $src, $zero || or $dst, $zero, $src
+ SrcSubIdx = DstSubIdx = 0; // No sub-registers.
+
+ // addu $dst, $src, $zero || addu $dst, $zero, $src
+ // or $dst, $src, $zero || or $dst, $zero, $src
if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
if (MI.getOperand(1).getReg() == Mips::ZERO) {
DstReg = MI.getOperand(0).getReg();
// mov $fpDst, $fpSrc
// mfc $gpDst, $fpSrc
// mtc $fpDst, $gpSrc
- if (MI.getOpcode() == Mips::FMOV_SO32 || MI.getOpcode() == Mips::FMOV_AS32 ||
- MI.getOpcode() == Mips::FMOV_D32 || MI.getOpcode() == Mips::MFC1A ||
- MI.getOpcode() == Mips::MFC1 || MI.getOpcode() == Mips::MTC1A ||
- MI.getOpcode() == Mips::MTC1 ) {
+ if (MI.getOpcode() == Mips::FMOV_S32 ||
+ MI.getOpcode() == Mips::FMOV_D32 ||
+ MI.getOpcode() == Mips::MFC1 ||
+ MI.getOpcode() == Mips::MTC1 ||
+ MI.getOpcode() == Mips::MOVCCRToCCR) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
- // addiu $dst, $src, 0
+ // addiu $dst, $src, 0
if (MI.getOpcode() == Mips::ADDiu) {
- if ((MI.getOperand(1).isRegister()) && (isZeroImm(MI.getOperand(2)))) {
+ if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
}
+
return false;
}
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned MipsInstrInfo::
-isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
+isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
{
if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
- (MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) {
- if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
- (MI->getOperand(1).isImmediate()) && // the imm is zero
+ (MI->getOpcode() == Mips::LDC1)) {
+ if ((MI->getOperand(2).isFI()) && // is a stack slot
+ (MI->getOperand(1).isImm()) && // the imm is zero
(isZeroImm(MI->getOperand(1)))) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned MipsInstrInfo::
-isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
+isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
{
if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
- (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
- if ((MI->getOperand(0).isFrameIndex()) && // is a stack slot
- (MI->getOperand(1).isImmediate()) && // the imm is zero
+ (MI->getOpcode() == Mips::SDC1)) {
+ if ((MI->getOperand(2).isFI()) && // is a stack slot
+ (MI->getOperand(1).isImm()) && // the imm is zero
(isZeroImm(MI->getOperand(1)))) {
- FrameIndex = MI->getOperand(0).getIndex();
- return MI->getOperand(2).getReg();
+ FrameIndex = MI->getOperand(2).getIndex();
+ return MI->getOperand(0).getReg();
}
}
return 0;
void MipsInstrInfo::
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
{
- BuildMI(MBB, MI, get(Mips::NOP));
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+ BuildMI(MBB, MI, DL, get(Mips::NOP));
}
-void MipsInstrInfo::
+bool MipsInstrInfo::
copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (DestRC != SrcRC) {
+
+ // Copy to/from FCR31 condition register
if ((DestRC == Mips::CPURegsRegisterClass) &&
- (SrcRC == Mips::FGR32RegisterClass))
- BuildMI(MBB, I, get(Mips::MFC1), DestReg).addReg(SrcReg);
+ (SrcRC == Mips::CCRRegisterClass))
+ BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
+ else if ((DestRC == Mips::CCRRegisterClass) &&
+ (SrcRC == Mips::CPURegsRegisterClass))
+ BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
+
+ // Moves between coprocessors and cpu
else if ((DestRC == Mips::CPURegsRegisterClass) &&
- (SrcRC == Mips::AFGR32RegisterClass))
- BuildMI(MBB, I, get(Mips::MFC1A), DestReg).addReg(SrcReg);
+ (SrcRC == Mips::FGR32RegisterClass))
+ BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
else if ((DestRC == Mips::FGR32RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass))
- BuildMI(MBB, I, get(Mips::MTC1), DestReg).addReg(SrcReg);
- else if ((DestRC == Mips::AFGR32RegisterClass) &&
- (SrcRC == Mips::CPURegsRegisterClass))
- BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
- else if ((SrcRC == Mips::CCRRegisterClass) &&
- (SrcReg == Mips::FCR31))
- return; // This register is used implicitly, no copy needed.
- else if ((DestRC == Mips::CCRRegisterClass) &&
- (DestReg == Mips::FCR31))
- return; // This register is used implicitly, no copy needed.
- else
- assert (0 && "DestRC != SrcRC, Can't copy this register");
+ BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
+
+ // Move from/to Hi/Lo registers
+ else if ((DestRC == Mips::HILORegisterClass) &&
+ (SrcRC == Mips::CPURegsRegisterClass)) {
+ unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
+ BuildMI(MBB, I, DL, get(Opc), DestReg);
+ } else if ((SrcRC == Mips::HILORegisterClass) &&
+ (DestRC == Mips::CPURegsRegisterClass)) {
+ unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
+ BuildMI(MBB, I, DL, get(Opc), DestReg);
+
+ // Can't copy this register
+ } else
+ return false;
+
+ return true;
}
if (DestRC == Mips::CPURegsRegisterClass)
- BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
+ BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
.addReg(SrcReg);
else if (DestRC == Mips::FGR32RegisterClass)
- BuildMI(MBB, I, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg);
- else if (DestRC == Mips::AFGR32RegisterClass)
- BuildMI(MBB, I, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
else if (DestRC == Mips::AFGR64RegisterClass)
- BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
+ else if (DestRC == Mips::CCRRegisterClass)
+ BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
else
- assert (0 && "Can't copy this register");
+ // Can't copy this register
+ return false;
+
+ return true;
}
void MipsInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, bool isKill, int FI,
- const TargetRegisterClass *RC) const
-{
+ unsigned SrcReg, bool isKill, int FI,
+ const TargetRegisterClass *RC) const {
unsigned Opc;
+
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (RC == Mips::CPURegsRegisterClass)
Opc = Mips::SW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::SWC1;
- else if (RC == Mips::AFGR32RegisterClass)
- Opc = Mips::SWC1A;
- else if (RC == Mips::AFGR64RegisterClass)
+ else {
+ assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::SDC1;
- else
- assert(0 && "Can't store this register to stack slot");
-
- BuildMI(MBB, I, get(Opc)).addReg(SrcReg, false, false, isKill)
+ }
+
+ BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
}
Opc = Mips::SW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::SWC1;
- else if (RC == Mips::AFGR32RegisterClass)
- Opc = Mips::SWC1A;
- else if (RC == Mips::AFGR64RegisterClass)
+ else {
+ assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::SDC1;
- else
- assert(0 && "Can't store this register");
-
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
- .addReg(SrcReg, false, false, isKill);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
}
+
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
+ .addReg(SrcReg, getKillRegState(isKill));
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
return;
}
Opc = Mips::LW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::LWC1;
- else if (RC == Mips::AFGR32RegisterClass)
- Opc = Mips::LWC1A;
- else if (RC == Mips::AFGR64RegisterClass)
+ else {
+ assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::LDC1;
- else
- assert(0 && "Can't load this register from stack slot");
-
- BuildMI(MBB, I, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
+ }
+
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+ BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
}
void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc;
if (RC == Mips::CPURegsRegisterClass)
Opc = Mips::LW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::LWC1;
- else if (RC == Mips::AFGR32RegisterClass)
- Opc = Mips::LWC1A;
- else if (RC == Mips::AFGR64RegisterClass)
+ else {
+ assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::LDC1;
- else
- assert(0 && "Can't load this register");
-
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
}
+
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB.addOperand(Addr[i]);
NewMIs.push_back(MIB);
return;
}
MachineInstr *MipsInstrInfo::
-foldMemoryOperand(MachineFunction &MF,
- MachineInstr* MI,
- SmallVectorImpl<unsigned> &Ops, int FI) const
+foldMemoryOperandImpl(MachineFunction &MF,
+ MachineInstr* MI,
+ const SmallVectorImpl<unsigned> &Ops, int FI) const
{
if (Ops.size() != 1) return NULL;
switch (MI->getOpcode()) {
case Mips::ADDu:
- if ((MI->getOperand(0).isRegister()) &&
- (MI->getOperand(1).isRegister()) &&
+ if ((MI->getOperand(0).isReg()) &&
+ (MI->getOperand(1).isReg()) &&
(MI->getOperand(1).getReg() == Mips::ZERO) &&
- (MI->getOperand(2).isRegister())) {
+ (MI->getOperand(2).isReg())) {
if (Ops[0] == 0) { // COPY -> STORE
unsigned SrcReg = MI->getOperand(2).getReg();
bool isKill = MI->getOperand(2).isKill();
- NewMI = BuildMI(MF, get(Mips::SW)).addFrameIndex(FI)
- .addImm(0).addReg(SrcReg, false, false, isKill);
+ bool isUndef = MI->getOperand(2).isUndef();
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
+ .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+ .addImm(0).addFrameIndex(FI);
} else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(Mips::LW))
- .addReg(DstReg, true, false, false, isDead)
+ bool isUndef = MI->getOperand(0).isUndef();
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
+ getUndefRegState(isUndef))
.addImm(0).addFrameIndex(FI);
}
}
break;
- case Mips::FMOV_SO32:
- case Mips::FMOV_AS32:
+ case Mips::FMOV_S32:
case Mips::FMOV_D32:
- if ((MI->getOperand(0).isRegister()) &&
- (MI->getOperand(1).isRegister())) {
+ if ((MI->getOperand(0).isReg()) &&
+ (MI->getOperand(1).isReg())) {
const TargetRegisterClass
*RC = RI.getRegClass(MI->getOperand(0).getReg());
unsigned StoreOpc, LoadOpc;
if (RC == Mips::FGR32RegisterClass) {
LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
- } else if (RC == Mips::AFGR32RegisterClass) {
- LoadOpc = Mips::LWC1A; StoreOpc = Mips::SWC1A;
- } else if (RC == Mips::AFGR64RegisterClass) {
+ } else {
+ assert(RC == Mips::AFGR64RegisterClass);
LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
- } else
- assert(0 && "foldMemoryOperand register unknown");
+ }
if (Ops[0] == 0) { // COPY -> STORE
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = BuildMI(MF, get(StoreOpc)).addFrameIndex(FI)
- .addImm(0).addReg(SrcReg, false, false, isKill);
+ bool isUndef = MI->getOperand(2).isUndef();
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
+ .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+ .addImm(0).addFrameIndex(FI) ;
} else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(LoadOpc))
- .addReg(DstReg, true, false, false, isDead)
+ bool isUndef = MI->getOperand(0).isUndef();
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
+ .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
+ getUndefRegState(isUndef))
.addImm(0).addFrameIndex(FI);
}
}
bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
- std::vector<MachineOperand> &Cond) const
+ SmallVectorImpl<MachineOperand> &Cond,
+ bool AllowModify) const
{
// If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end();
unsigned SecondLastOpc = SecondLastInst->getOpcode();
Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
- if (SecondLastOpc != Mips::COND_INVALID && LastOpc == Mips::J) {
+ if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
int SecondNumOp = SecondLastInst->getNumOperands();
TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
- I->eraseFromParent();
+ if (AllowModify)
+ I->eraseFromParent();
return false;
}
unsigned MipsInstrInfo::
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
- MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond)
- const
-{
+ MachineBasicBlock *FBB,
+ const SmallVectorImpl<MachineOperand> &Cond) const {
+ // FIXME this should probably have a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
if (FBB == 0) { // One way branch.
if (Cond.empty()) {
// Unconditional branch?
- BuildMI(&MBB, get(Mips::J)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
} else {
// Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3)
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
+ BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
.addReg(Cond[2].getReg())
.addMBB(TBB);
else
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
+ BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
.addMBB(TBB);
}
const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3)
- BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
+ BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
.addMBB(TBB);
else
- BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
+ BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
- BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
+ BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
return 2;
}
return 2;
}
-/// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
+/// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
/// fall-through into its successor block.
bool MipsInstrInfo::
-BlockHasNoFallThrough(MachineBasicBlock &MBB) const
+BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
{
if (MBB.empty()) return false;
/// ReverseBranchCondition - Return the inverse opcode of the
/// specified Branch instruction.
bool MipsInstrInfo::
-ReverseBranchCondition(std::vector<MachineOperand> &Cond) const
+ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
{
assert( (Cond.size() == 3 || Cond.size() == 2) &&
"Invalid Mips branch condition!");
Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
return false;
}
+
+/// getGlobalBaseReg - Return a virtual register initialized with the
+/// the global base register value. Output instructions required to
+/// initialize the register in the function entry block, if necessary.
+///
+unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
+ MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
+ unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
+ if (GlobalBaseReg != 0)
+ return GlobalBaseReg;
+
+ // Insert the set of GlobalBaseReg into the first MBB of the function
+ MachineBasicBlock &FirstMBB = MF->front();
+ MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+ MachineRegisterInfo &RegInfo = MF->getRegInfo();
+ const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
+
+ GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
+ bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
+ Mips::CPURegsRegisterClass,
+ Mips::CPURegsRegisterClass);
+ assert(Ok && "Couldn't assign to global base register!");
+ RegInfo.addLiveIn(Mips::GP);
+
+ MipsFI->setGlobalBaseReg(GlobalBaseReg);
+ return GlobalBaseReg;
+}
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