// TODO: Add the subtarget support on this constructor
MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
- : TargetInstrInfo(MipsInsts, array_lengthof(MipsInsts)),
+ : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
TM(tm), RI(*this) {}
static bool isZeroImm(const MachineOperand &op) {
- return op.isImmediate() && op.getImmedValue() == 0;
+ return op.isImmediate() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
(MI->getOperand(1).isImmediate()) && // the imm is zero
(isZeroImm(MI->getOperand(1))))
{
- FrameIndex = MI->getOperand(2).getFrameIndex();
+ FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
}
(MI->getOperand(1).isImmediate()) && // the imm is zero
(isZeroImm(MI->getOperand(1))))
{
- FrameIndex = MI->getOperand(0).getFrameIndex();
+ FrameIndex = MI->getOperand(0).getIndex();
return MI->getOperand(2).getReg();
}
}
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
- if (!isBranch(LastInst->getOpcode()))
+ if (!LastInst->getDesc().isBranch())
return true;
// Unconditional branch
if (LastOpc == Mips::J) {
- TBB = LastInst->getOperand(0).getMachineBasicBlock();
+ TBB = LastInst->getOperand(0).getMBB();
return false;
}
if (LastOpc != Mips::COND_INVALID) {
int LastNumOp = LastInst->getNumOperands();
- TBB = LastInst->getOperand(LastNumOp-1).getMachineBasicBlock();
+ TBB = LastInst->getOperand(LastNumOp-1).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
for (int i=0; i<LastNumOp-1; i++) {
if (SecondLastOpc != Mips::COND_INVALID && LastOpc == Mips::J) {
int SecondNumOp = SecondLastInst->getNumOperands();
- TBB = SecondLastInst->getOperand(SecondNumOp-1).getMachineBasicBlock();
+ TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
for (int i=0; i<SecondNumOp-1; i++) {
Cond.push_back(SecondLastInst->getOperand(i));
}
- FBB = LastInst->getOperand(0).getMachineBasicBlock();
+ FBB = LastInst->getOperand(0).getMBB();
return false;
}
// If the block ends with two unconditional branches, handle it. The last
// one is not executed, so remove it.
if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
- TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
+ TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
I->eraseFromParent();
return false;
} else {
// Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
- if (TID.numOperands == 3)
+ if (TID.getNumOperands() == 3)
BuildMI(&MBB, TID).addReg(Cond[1].getReg())
.addReg(Cond[2].getReg())
.addMBB(TBB);
// Two-way Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
- if (TID.numOperands == 3)
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
- .addReg(Cond[2].getReg())
+ if (TID.getNumOperands() == 3)
+ BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
.addMBB(TBB);
else
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
- .addMBB(TBB);
+ BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
return 2;
}
+void MipsInstrInfo::
+copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const {
+ if (DestRC != SrcRC) {
+ cerr << "Not yet supported!";
+ abort();
+ }
+
+ if (DestRC == Mips::CPURegsRegisterClass)
+ BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
+ .addReg(SrcReg);
+ else
+ assert (0 && "Can't copy this register");
+}
+
+void MipsInstrInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned SrcReg, bool isKill, int FI,
+ const TargetRegisterClass *RC) const
+{
+ if (RC == Mips::CPURegsRegisterClass)
+ BuildMI(MBB, I, get(Mips::SW)).addReg(SrcReg, false, false, isKill)
+ .addImm(0).addFrameIndex(FI);
+ else
+ assert(0 && "Can't store this register to stack slot");
+}
+
+void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ if (RC != Mips::CPURegsRegisterClass)
+ assert(0 && "Can't store this register");
+ MachineInstrBuilder MIB = BuildMI(get(Mips::SW))
+ .addReg(SrcReg, false, false, isKill);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ return;
+}
+
+void MipsInstrInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned DestReg, int FI,
+ const TargetRegisterClass *RC) const
+{
+ if (RC == Mips::CPURegsRegisterClass)
+ BuildMI(MBB, I, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
+ else
+ assert(0 && "Can't load this register from stack slot");
+}
+
+void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ if (RC != Mips::CPURegsRegisterClass)
+ assert(0 && "Can't load this register");
+ MachineInstrBuilder MIB = BuildMI(get(Mips::LW), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ return;
+}
+
+MachineInstr *MipsInstrInfo::
+foldMemoryOperand(MachineFunction &MF,
+ MachineInstr* MI,
+ SmallVectorImpl<unsigned> &Ops, int FI) const
+{
+ if (Ops.size() != 1) return NULL;
+
+ MachineInstr *NewMI = NULL;
+
+ switch (MI->getOpcode())
+ {
+ case Mips::ADDu:
+ if ((MI->getOperand(0).isRegister()) &&
+ (MI->getOperand(1).isRegister()) &&
+ (MI->getOperand(1).getReg() == Mips::ZERO) &&
+ (MI->getOperand(2).isRegister()))
+ {
+ if (Ops[0] == 0) // COPY -> STORE
+ NewMI = BuildMI(get(Mips::SW)).addFrameIndex(FI)
+ .addImm(0).addReg(MI->getOperand(2).getReg());
+ else // COPY -> LOAD
+ NewMI = BuildMI(get(Mips::LW), MI->getOperand(0)
+ .getReg()).addImm(0).addFrameIndex(FI);
+ }
+ break;
+ }
+
+ if (NewMI)
+ NewMI->copyKillDeadInfo(MI);
+ return NewMI;
+}
+
unsigned MipsInstrInfo::
RemoveBranch(MachineBasicBlock &MBB) const
{
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