- Add sugregister logic to handle f64=(f32,f32).

[oota-llvm.git] / lib / Target / Mips / MipsInstrInfo.td

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index e6ac6fbbf312173c2494843c5004cd22913d0a9b..46cf43e422db90935e0e0c217f06b9ebcb8cac80 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -224,7 +224,7 @@ class LoadUpper<bits<6> op, string instr_asm>:
       [], IIAlu>;
 
 // Memory Load/Store
-let isSimpleLoad = 1, hasDelaySlot = 1 in
+let canFoldAsLoad = 1, hasDelaySlot = 1 in
 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
   FI< op,
       (outs CPURegs:$dst),
@@ -417,7 +417,7 @@ def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally 
 // replace it for real supported nodes into EmitInstrWithCustomInserter
-let usesCustomDAGSchedInserter = 1 in {
+let usesCustomInserter = 1 in {
   class PseudoSelCC<RegisterClass RC, string asmstr>: 
     MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr, 
     [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
@@ -518,10 +518,10 @@ let Uses = [LO] in
 
 /// Sign Ext In Register Instructions.
 let Predicates = [HasSEInReg] in {
-  let shamt = 0x10, rs = 0 in 
+  let shamt = 0x10, rs = 0 in
     def SEB : SignExtInReg<0x21, "seb", i8>;
 
-  let shamt = 0x18, rs = 0 in 
+  let shamt = 0x18, rs = 0 in
     def SEH : SignExtInReg<0x20, "seh", i16>;
 }