Fix a ValueTracking rule: RHS means operand 1, not 0. Add a simple

[oota-llvm.git] / lib / Target / Mips / MipsInstrInfo.td

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 2bd5ec3e3b3d10aa2020b01527a74250bc38bcb0..e30dfbf29e97c1fa012a598e3cc19ee2e1cef56e 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -85,21 +85,21 @@ def mem : Operand<i32> {
 
 // Transformation Function - get the lower 16 bits.
 def LO16 : SDNodeXForm<imm, [{
-  return getI32Imm((unsigned)N->getValue() & 0xFFFF);
+  return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
 }]>;
 
 // Transformation Function - get the higher 16 bits.
 def HI16 : SDNodeXForm<imm, [{
-  return getI32Imm((unsigned)N->getValue() >> 16);
+  return getI32Imm((unsigned)N->getZExtValue() >> 16);
 }]>;
 
 // Node immediate fits as 16-bit sign extended on target immediate.
 // e.g. addi, andi
 def immSExt16  : PatLeaf<(imm), [{
   if (N->getValueType(0) == MVT::i32)
-    return (int32_t)N->getValue() == (short)N->getValue();
+    return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
   else
-    return (int64_t)N->getValue() == (short)N->getValue();
+    return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
 }]>;
 
 // Node immediate fits as 16-bit zero extended on target immediate.
@@ -108,14 +108,14 @@ def immSExt16  : PatLeaf<(imm), [{
 // e.g. addiu, sltiu
 def immZExt16  : PatLeaf<(imm), [{
   if (N->getValueType(0) == MVT::i32)
-    return (uint32_t)N->getValue() == (unsigned short)N->getValue();
+    return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
   else
-    return (uint64_t)N->getValue() == (unsigned short)N->getValue();
+    return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
 }], LO16>;
 
 // shamt field must fit in 5 bits.
 def immZExt5 : PatLeaf<(imm), [{
-  return N->getValue() == ((N->getValue()) & 0x1f) ;
+  return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
 }]>;
 
 // Mips Address Mode! SDNode frameindex could possibily be a match
@@ -224,7 +224,7 @@ class LoadUpper<bits<6> op, string instr_asm>:
       [], IIAlu>;
 
 // Memory Load/Store
-let isSimpleLoad = 1, hasDelaySlot = 1 in
+let canFoldAsLoad = 1, hasDelaySlot = 1 in
 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
   FI< op,
       (outs CPURegs:$dst),
@@ -393,10 +393,10 @@ class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
 let Defs = [SP], Uses = [SP] in {
 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
                                   "!ADJCALLSTACKDOWN $amt",
-                                  [(callseq_start imm:$amt)]>;
+                                  [(callseq_start timm:$amt)]>;
 def ADJCALLSTACKUP   : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
                                   "!ADJCALLSTACKUP $amt1",
-                                  [(callseq_end imm:$amt1, imm:$amt2)]>;
+                                  [(callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
 // Some assembly macros need to avoid pseudoinstructions and assembler