remove blanks, and some code format

[oota-llvm.git] / lib / Target / Mips / MipsMCInstLower.cpp

diff --git a/lib/Target/Mips/MipsMCInstLower.cpp b/lib/Target/Mips/MipsMCInstLower.cpp
index 541386543880d3259a61d2b68fd9e76d604c2a63..be6529836387c934993859f6ccb271f4f987c701 100644 (file)
--- a/lib/Target/Mips/MipsMCInstLower.cpp
+++ b/lib/Target/Mips/MipsMCInstLower.cpp
@@ -37,7 +37,7 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
   const MCSymbol *Symbol;
 
   switch(MO.getTargetFlags()) {
-  default:                   assert(0 && "Invalid target flag!");
+  default:                   llvm_unreachable("Invalid target flag!");
   case MipsII::MO_NO_FLAG:   Kind = MCSymbolRefExpr::VK_None; break;
   case MipsII::MO_GPREL:     Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
   case MipsII::MO_GOT_CALL:  Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
@@ -89,7 +89,7 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
   default:
     llvm_unreachable("<unknown operand type>");
   }
-  
+
   const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, Ctx);
 
   if (!Offset)
@@ -97,7 +97,7 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
 
   // Assume offset is never negative.
   assert(Offset > 0);
-   
+
   const MCConstantExpr *OffsetExpr =  MCConstantExpr::Create(Offset, Ctx);
   const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, Ctx);
   return MCOperand::CreateExpr(AddExpr);
@@ -148,7 +148,7 @@ void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI,
   MCInst Sw;
 
   if (Offset >= 0x8000) {
-    unsigned Hi = (Offset >> 16) + ((Offset & 0x8000) != 0); 
+    unsigned Hi = (Offset >> 16) + ((Offset & 0x8000) != 0);
     Offset &= 0xffff;
     Reg = Mips::AT;
 
@@ -163,7 +163,7 @@ void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI,
     MCInsts[1].addOperand(MCOperand::CreateReg(Mips::AT));
     MCInsts[1].addOperand(MCOperand::CreateReg(Mips::SP));
   }
-  
+
   Sw.setOpcode(Mips::SW);
   Sw.addOperand(MCOperand::CreateReg(Mips::GP));
   Sw.addOperand(MCOperand::CreateReg(Reg));
@@ -172,13 +172,11 @@ void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI,
 }
 
 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
-                                                   unsigned offset) const {
+                                        unsigned offset) const {
   MachineOperandType MOTy = MO.getType();
-  
+
   switch (MOTy) {
-  default:
-    assert(0 && "unknown operand type");
-    break;
+  default: llvm_unreachable("unknown operand type");
   case MachineOperand::MO_Register:
     // Ignore all implicit register operands.
     if (MO.isImplicit()) break;
@@ -201,7 +199,7 @@ MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
 
 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   OutMI.setOpcode(MI->getOpcode());
-  
+
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     MCOperand MCOp = LowerOperand(MO);
@@ -212,8 +210,8 @@ void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
 }
 
 void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
-                                                         SmallVector<MCInst,
-                                                         4>& MCInsts) {
+                                              SmallVector<MCInst,
+                                              4>& MCInsts) {
   unsigned Opc = MI->getOpcode();
   MCInst Instr1, Instr2, Instr3, Move;
 
@@ -315,7 +313,7 @@ void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
   }
   default:
     // FIXME: need to add others
-    assert(0 && "unaligned instruction not processed");
+    llvm_unreachable("unaligned instruction not processed");
   }
 
   MCInsts.push_back(Instr1);
@@ -323,3 +321,29 @@ void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
   if (!TwoInstructions) MCInsts.push_back(Instr3);
 }
 
+// Convert
+//  "setgp01 $reg"
+// to
+//  "lui   $reg, %hi(_gp_disp)"
+//  "addiu $reg, $reg, %lo(_gp_disp)"
+void MipsMCInstLower::LowerSETGP01(const MachineInstr *MI,
+                                   SmallVector<MCInst, 4>& MCInsts) {
+  const MachineOperand &MO = MI->getOperand(0);
+  assert(MO.isReg());
+  MCOperand RegOpnd = MCOperand::CreateReg(MO.getReg());
+  StringRef SymName("_gp_disp");
+  const MCSymbol *Sym = Ctx.GetOrCreateSymbol(SymName);
+  const MCSymbolRefExpr *MCSym;
+
+  MCInsts.resize(2);
+
+  MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, Ctx);
+  MCInsts[0].setOpcode(Mips::LUi);
+  MCInsts[0].addOperand(RegOpnd);
+  MCInsts[0].addOperand(MCOperand::CreateExpr(MCSym));
+  MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, Ctx);
+  MCInsts[1].setOpcode(Mips::ADDiu);
+  MCInsts[1].addOperand(RegOpnd);
+  MCInsts[1].addOperand(RegOpnd);
+  MCInsts[1].addOperand(MCOperand::CreateExpr(MCSym));
+}