ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics...

[oota-llvm.git] / lib / Target / Mips / MipsRegisterInfo.td

diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index 0a7a69e8e071227d520170ca0a135c73a48c16ec..10956aa7413c7906eea738900903bbd93a595092 100644 (file)
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -126,6 +126,10 @@ let Namespace = "Mips" in {
   def D14 : AFPR<28, "F28", [F28, F29]>, DwarfRegNum<[60]>;
   def D15 : AFPR<30, "F30", [F30, F31]>, DwarfRegNum<[62]>;
 
+  // Hi/Lo registers
+  def HI  : Register<"hi">, DwarfRegNum<[64]>;
+  def LO  : Register<"lo">, DwarfRegNum<[65]>;
+
   // Status flags register
   def FCR31 : Register<"FCR31">;
 }
@@ -233,3 +237,7 @@ def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]> {
   let CopyCost = -1;  // Don't allow copying of status registers.
 }
 
+def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]> {
+  //let CopyCost = -1;  // Don't allow copying of hi/lo registers.
+}
+