-//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
+//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
let Namespace = "Mips";
}
+class MipsRegWithSubRegs<string n, list<Register> subregs>
+ : RegisterWithSubRegs<n, subregs> {
+ field bits<5> Num;
+ let Namespace = "Mips";
+}
+
// Mips CPU Registers
class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
let Num = num;
}
// Mips 64-bit (aliased) FPU Registers
-class AFPR<bits<5> num, string n, list<Register> aliases> : MipsReg<n> {
+let Namespace = "Mips" in {
+def sub_fpeven : SubRegIndex;
+def sub_fpodd : SubRegIndex;
+}
+class AFPR<bits<5> num, string n, list<Register> subregs>
+ : MipsRegWithSubRegs<n, subregs> {
+ let Num = num;
+ let SubRegIndices = [sub_fpeven, sub_fpodd];
+}
+
+// Mips Hardware Registers
+class HWR<bits<5> num, string n> : MipsReg<n> {
let Num = num;
- let Aliases = aliases;
}
//===----------------------------------------------------------------------===//
def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
- def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>;
+ def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
-
+
/// Mips Single point precision FPU Registers
def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
-
+
/// Mips Double point precision FPU Registers (aliased
/// with the single precision to hold 64 bit values)
- def D0 : AFPR< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
- def D1 : AFPR< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
- def D2 : AFPR< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>;
- def D3 : AFPR< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>;
- def D4 : AFPR< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>;
- def D5 : AFPR<10, "F10", [F10, F11]>, DwarfRegNum<[42]>;
- def D6 : AFPR<12, "F12", [F12, F13]>, DwarfRegNum<[44]>;
- def D7 : AFPR<14, "F14", [F14, F15]>, DwarfRegNum<[46]>;
- def D8 : AFPR<16, "F16", [F16, F17]>, DwarfRegNum<[48]>;
- def D9 : AFPR<18, "F18", [F18, F19]>, DwarfRegNum<[50]>;
- def D10 : AFPR<20, "F20", [F20, F21]>, DwarfRegNum<[52]>;
- def D11 : AFPR<22, "F22", [F22, F23]>, DwarfRegNum<[54]>;
- def D12 : AFPR<24, "F24", [F24, F25]>, DwarfRegNum<[56]>;
- def D13 : AFPR<26, "F26", [F26, F27]>, DwarfRegNum<[58]>;
- def D14 : AFPR<28, "F28", [F28, F29]>, DwarfRegNum<[60]>;
- def D15 : AFPR<30, "F30", [F30, F31]>, DwarfRegNum<[62]>;
+ def D0 : AFPR< 0, "F0", [F0, F1]>;
+ def D1 : AFPR< 2, "F2", [F2, F3]>;
+ def D2 : AFPR< 4, "F4", [F4, F5]>;
+ def D3 : AFPR< 6, "F6", [F6, F7]>;
+ def D4 : AFPR< 8, "F8", [F8, F9]>;
+ def D5 : AFPR<10, "F10", [F10, F11]>;
+ def D6 : AFPR<12, "F12", [F12, F13]>;
+ def D7 : AFPR<14, "F14", [F14, F15]>;
+ def D8 : AFPR<16, "F16", [F16, F17]>;
+ def D9 : AFPR<18, "F18", [F18, F19]>;
+ def D10 : AFPR<20, "F20", [F20, F21]>;
+ def D11 : AFPR<22, "F22", [F22, F23]>;
+ def D12 : AFPR<24, "F24", [F24, F25]>;
+ def D13 : AFPR<26, "F26", [F26, F27]>;
+ def D14 : AFPR<28, "F28", [F28, F29]>;
+ def D15 : AFPR<30, "F30", [F30, F31]>;
+
+ // Hi/Lo registers
+ def HI : Register<"hi">, DwarfRegNum<[64]>;
+ def LO : Register<"lo">, DwarfRegNum<[65]>;
// Status flags register
- def FCR31 : Register<"FCR31">;
+ def FCR31 : Register<"31">;
+
+ // Hardware register $29
+ def HWR29 : Register<"29">;
}
//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
-def CPURegs : RegisterClass<"Mips", [i32], 32,
+def CPURegs : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
- [V0, V1, A0, A1, A2, A3,
+ V0, V1, A0, A1, A2, A3,
// Not preserved across procedure calls
- T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
+ T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
// Callee save
S0, S1, S2, S3, S4, S5, S6, S7,
// Reserved
- ZERO, AT, K0, K1, GP, SP, FP, RA]>
-{
- let MethodProtos = [{
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- CPURegsClass::iterator
- CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
- // The last 8 registers on the list above are reserved
- return end()-8;
- }
- }];
-}
+ ZERO, AT, K0, K1, GP, SP, FP, RA)>;
-// * 64bit fp:
-// - FGR64 = 32 64-bit registers (default mode)
-// - AFGR32/AFGR64 = 16 even 32-bit registers (32-bit compatible mode) for
-// single and double access.
-// * 32bit fp:
-// - AFGR32/AFGR64 = 16 even 32-bit registers - single and double
-// - FGR32 = 32 32-bit registers (within single-only mode)
-def FGR32 : RegisterClass<"Mips", [f32], 32,
- // Return Values and Arguments
- [F0, F1, F2, F3, F12, F13, F14, F15,
- // Not preserved across procedure calls
- F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
- // Callee save
- F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
- // Reserved
- F31]>
-{
- let MethodProtos = [{
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- FGR32Class::iterator
- FGR32Class::allocation_order_end(const MachineFunction &MF) const {
- // The last register on the list above is reserved
- return end()-1;
- }
- }];
-}
-
-def AFGR32 : RegisterClass<"Mips", [f32], 32,
- // Return Values and Arguments
- [F0, F2, F12, F14,
- // Not preserved across procedure calls
- F4, F6, F8, F10, F16, F18,
- // Callee save
- F20, F22, F24, F26, F28, F30,
- // Reserved
- F31]>
-{
- let MethodProtos = [{
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- AFGR32Class::iterator
- AFGR32Class::allocation_order_end(const MachineFunction &MF) const {
- // The last register on the list above is reserved
- return end()-1;
- }
- }];
-}
+// 64bit fp:
+// * FGR64 - 32 64-bit registers
+// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
+//
+// 32bit fp:
+// * FGR32 - 16 32-bit even registers
+// * FGR32 - 32 32-bit registers (single float only mode)
+def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
-def AFGR64 : RegisterClass<"Mips", [f64], 64,
+def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Return Values and Arguments
- [D0, D1, D6, D7,
+ D0, D1, D6, D7,
// Not preserved across procedure calls
- D2, D3, D4, D5, D8, D9,
+ D2, D3, D4, D5, D8, D9,
// Callee save
D10, D11, D12, D13, D14,
// Reserved
- D15]>
-{
- let MethodProtos = [{
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- AFGR64Class::iterator
- AFGR64Class::allocation_order_end(const MachineFunction &MF) const {
- // The last register on the list above is reserved
- return end()-1;
- }
- }];
+ D15)> {
+ let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
}
-def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]> {
- let CopyCost = -1; // Don't allow copying of status registers.
-}
+// Condition Register for floating point operations
+def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>;
+
+// Hi/Lo Registers
+def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>;
+// Hardware registers
+def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;
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