[SystemZ] Prefer LHI;ST... over LAY;MV...

[oota-llvm.git] / lib / Target / Mips / MipsSEFrameLowering.cpp

diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp
index d9e0fa4aac4b49ee0718f2bbb5a3dfa1f5fcdfde..ab69453391be69e59b3414a97e44185547431656 100644 (file)
--- a/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -70,31 +70,23 @@ bool ExpandPseudo::expand() {
 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
   switch(I->getOpcode()) {
   case Mips::LOAD_CCOND_DSP:
-  case Mips::LOAD_CCOND_DSP_P8:
     expandLoadCCond(MBB, I);
     break;
   case Mips::STORE_CCOND_DSP:
-  case Mips::STORE_CCOND_DSP_P8:
     expandStoreCCond(MBB, I);
     break;
-  case Mips::LOAD_AC64:
-  case Mips::LOAD_AC64_P8:
-  case Mips::LOAD_AC_DSP:
-  case Mips::LOAD_AC_DSP_P8:
+  case Mips::LOAD_ACC64:
+  case Mips::LOAD_ACC64DSP:
     expandLoadACC(MBB, I, 4);
     break;
-  case Mips::LOAD_AC128:
-  case Mips::LOAD_AC128_P8:
+  case Mips::LOAD_ACC128:
     expandLoadACC(MBB, I, 8);
     break;
-  case Mips::STORE_AC64:
-  case Mips::STORE_AC64_P8:
-  case Mips::STORE_AC_DSP:
-  case Mips::STORE_AC_DSP_P8:
+  case Mips::STORE_ACC64:
+  case Mips::STORE_ACC64DSP:
     expandStoreACC(MBB, I, 4);
     break;
-  case Mips::STORE_AC128:
-  case Mips::STORE_AC128_P8:
+  case Mips::STORE_ACC128:
     expandStoreACC(MBB, I, 8);
     break;
   case TargetOpcode::COPY:
@@ -210,10 +202,10 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
 bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
   unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
 
-  if (Mips::ACRegsDSPRegClass.contains(Dst, Src))
+  if (Mips::ACC64DSPRegClass.contains(Dst, Src))
     return expandCopyACC(MBB, I, Dst, Src, 4);
 
-  if (Mips::ACRegs128RegClass.contains(Dst, Src))
+  if (Mips::ACC128RegClass.contains(Dst, Src))
     return expandCopyACC(MBB, I, Dst, Src, 8);
 
   return false;
@@ -321,9 +313,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
       // one for each of the paired single precision registers.
       if (Mips::AFGR64RegClass.contains(Reg)) {
         unsigned Reg0 =
-            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
+            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
         unsigned Reg1 =
-            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
+            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
 
         if (!STI.isLittle())
           std::swap(Reg0, Reg1);