Compute feature bits at time of MCSubtargetInfo initialization.

[oota-llvm.git] / lib / Target / Mips / MipsSchedule.td

diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td
index bb7d5f1a8838d1eed749b7ba1cbff75684cef4ca..00be8ee94431d5fdb79c575db7de27fe164b0065 100644 (file)
--- a/lib/Target/Mips/MipsSchedule.td
+++ b/lib/Target/Mips/MipsSchedule.td
@@ -1,21 +1,21 @@
-//===- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
+//===- MipsSchedule.td - Mips Scheduling Definitions -------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Functional units across Mips chips sets. Based on GCC/Mips backend files.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 def ALU     : FuncUnit;
 def IMULDIV : FuncUnit;
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for Mips
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 def IIAlu              : InstrItinClass;
 def IILoad             : InstrItinClass;
 def IIStore            : InstrItinClass;
@@ -37,9 +37,9 @@ def IIFsqrtDouble      : InstrItinClass;
 def IIFrecipFsqrtStep  : InstrItinClass;
 def IIPseudo           : InstrItinClass;
 
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 // Mips Generic instruction itineraries.
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<IIAlu              , [InstrStage<1,  [ALU]>]>,
   InstrItinData<IILoad             , [InstrStage<3,  [ALU]>]>,