#ifndef MIPSSUBTARGET_H
#define MIPSSUBTARGET_H
-#include "MCTargetDesc/MipsReginfo.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetSubtargetInfo.h"
-
#include <string>
#define GET_SUBTARGETINFO_HEADER
};
protected:
-
enum MipsArchEnum {
- Mips32, Mips32r2, Mips64, Mips64r2
+ Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
+ Mips64r2, Mips64r6
};
// Mips architecture version
// IsFP64bit - The target processor has 64-bit floating point registers.
bool IsFP64bit;
+ // IsNan2008 - IEEE 754-2008 NaN encoding.
+ bool IsNaN2008bit;
+
// IsFP64bit - General-purpose registers are 64 bits wide
bool IsGP64bit;
// HasVFPU - Processor has a vector floating point unit.
bool HasVFPU;
+ // CPU supports cnMIPS (Cavium Networks Octeon CPU).
+ bool HasCnMips;
+
// isLinux - Target system is Linux. Is false we consider ELFOS for now.
bool IsLinux;
/// Features related to the presence of specific instructions.
- // HasSEInReg - SEB and SEH (signext in register) instructions.
- bool HasSEInReg;
+ // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
+ bool HasMips3_32;
- // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
- bool HasCondMov;
+ // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
+ bool HasMips3_32r2;
- // HasSwap - Byte and half swap instructions.
- bool HasSwap;
+ // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
+ bool HasMips4_32;
- // HasBitCount - Count leading '1' and '0' bits.
- bool HasBitCount;
+ // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
+ bool HasMips4_32r2;
- // HasFPIdx -- Floating point indexed load/store instructions.
- bool HasFPIdx;
+ // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
+ bool HasMips5_32r2;
// InMips16 -- can process Mips16 instructions
bool InMips16Mode;
+ // Mips16 hard float
+ bool InMips16HardFloat;
+
// PreviousInMips16 -- the function we just processed was in Mips 16 Mode
bool PreviousInMips16Mode;
// Allow mixed Mips16 and Mips32 in one source file
bool AllowMixed16_32;
- InstrItineraryData InstrItins;
+ // Optimize for space by compiling all functions as Mips 16 unless
+ // it needs floating point. Functions needing floating point are
+ // compiled as Mips32
+ bool Os16;
+
+ // HasMSA -- supports MSA ASE.
+ bool HasMSA;
- // The instance to the register info section object
- MipsReginfo MRI;
+ InstrItineraryData InstrItins;
// Relocation Model
Reloc::Model RM;
MipsTargetMachine *TM;
+ Triple TargetTriple;
public:
- virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
- AntiDepBreakMode& Mode,
- RegClassVector& CriticalPathRCs) const;
+ bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+ AntiDepBreakMode& Mode,
+ RegClassVector& CriticalPathRCs) const override;
/// Only O32 and EABI supported right now.
bool isABI_EABI() const { return MipsABI == EABI; }
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
+ bool hasMips2() const { return MipsArchVersion >= Mips2; }
+ bool hasMips3() const { return MipsArchVersion >= Mips3; }
+ bool hasMips4_32() const { return HasMips4_32; }
+ bool hasMips4_32r2() const { return HasMips4_32r2; }
bool hasMips32() const { return MipsArchVersion >= Mips32; }
bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
MipsArchVersion == Mips64r2; }
+ bool hasMips32r6() const { return MipsArchVersion == Mips32r6 ||
+ MipsArchVersion == Mips64r6; }
bool hasMips64() const { return MipsArchVersion >= Mips64; }
bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
+ bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
+
+ bool hasCnMips() const { return HasCnMips; }
bool isLittle() const { return IsLittle; }
bool isFP64bit() const { return IsFP64bit; }
+ bool isNaN2008() const { return IsNaN2008bit; }
+ bool isNotFP64bit() const { return !IsFP64bit; }
bool isGP64bit() const { return IsGP64bit; }
bool isGP32bit() const { return !IsGP64bit; }
bool isSingleFloat() const { return IsSingleFloat; }
}
llvm_unreachable("Unexpected mode");
}
- bool inMips16ModeDefault() {
+ bool inMips16ModeDefault() const {
return InMips16Mode;
}
+ bool inMips16HardFloat() const {
+ return inMips16Mode() && InMips16HardFloat;
+ }
bool inMicroMipsMode() const { return InMicroMipsMode; }
bool hasDSP() const { return HasDSP; }
bool hasDSPR2() const { return HasDSPR2; }
+ bool hasMSA() const { return HasMSA; }
bool isLinux() const { return IsLinux; }
bool useSmallSection() const { return UseSmallSection; }
bool hasStandardEncoding() const { return !inMips16Mode(); }
+ bool mipsSEUsesSoftFloat() const;
+
+ bool enableLongBranchPass() const {
+ return hasStandardEncoding() || allowMixed16_32();
+ }
+
/// Features related to the presence of specific instructions.
- bool hasSEInReg() const { return HasSEInReg; }
- bool hasCondMov() const { return HasCondMov; }
- bool hasSwap() const { return HasSwap; }
- bool hasBitCount() const { return HasBitCount; }
- bool hasFPIdx() const { return HasFPIdx; }
+ bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
- bool allowMixed16_32() const { return AllowMixed16_32;};
+ const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
+ bool allowMixed16_32() const { return inMips16ModeDefault() |
+ AllowMixed16_32;}
- // Grab MipsRegInfo object
- const MipsReginfo &getMReginfo() const { return MRI; }
+ bool os16() const { return Os16;};
+
+ bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
+ bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
+
+ // for now constant islands are on for the whole compilation unit but we only
+ // really use them if in addition we are in mips16 mode
+ static bool useConstantIslands();
+
+ unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
// Grab relocation model
Reloc::Model getRelocationModel() const {return RM;}
/// \brief Reset the subtarget for the Mips target.
void resetSubtarget(MachineFunction *MF);
-
+ /// Does the system support unaligned memory access.
+ ///
+ /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
+ /// specify which component of the system provides it. Hardware, software, and
+ /// hybrid implementations are all valid.
+ bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
};
} // End llvm namespace
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