Print variable's display name in dwarf DIE.

[oota-llvm.git] / lib / Target / Mips / MipsSubtarget.h

diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index 2d5f2824e9021eabb3af6adbba0d34b021737049..656199a69ac3e560ae3a6d9c3a2581983592d089 100644 (file)
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -24,16 +24,17 @@ class Module;
 
 class MipsSubtarget : public TargetSubtarget {
 
+public:
+  enum MipsABIEnum {
+    O32, O64, N32, N64, EABI
+  }; 
+
 protected:
 
   enum MipsArchEnum {
-    Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
+    Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2
   };
 
-  enum MipsABIEnum {
-    O32, EABI
-  }; 
-  
   // Mips architecture version 
   MipsArchEnum MipsArchVersion;
 
@@ -54,11 +55,43 @@ protected:
   // IsFP64bit - General-purpose registers are 64 bits wide
   bool IsGP64bit;
 
-  // HasAllegrexVFPU - Allegrex processor has a vector floating point unit.
-  bool HasAllegrexVFPU;
+  // HasVFPU - Processor has a vector floating point unit.
+  bool HasVFPU;
+
+  // IsABICall - Enable SRV4 code for SVR4-style dynamic objects 
+  bool HasABICall;
+
+  // HasAbsoluteCall - Enable code that is not fully position-independent.
+  // Only works with HasABICall enabled.
+  bool HasAbsoluteCall;
 
-  // IsAllegrex - The target processor is a Allegrex core.
-  bool IsAllegrex;
+  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
+  bool IsLinux;
+
+  // Put global and static items less than or equal to SSectionThreshold 
+  // bytes into the small data or bss section. The default is 8.
+  unsigned SSectionThreshold;
+
+  /// Features related to the presence of specific instructions.
+  
+  // HasSEInReg - SEB and SEH (signext in register) instructions.
+  bool HasSEInReg;
+
+  // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
+  bool HasCondMov;
+
+  // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu) 
+  // instructions.
+  bool HasMulDivAdd;
+
+  // HasMinMax - MIN and MAX instructions.
+  bool HasMinMax;
+
+  // HasSwap - Byte and half swap instructions.
+  bool HasSwap;
+
+  // HasBitCount - Count leading '1' and '0' bits.
+  bool HasBitCount;
 
   InstrItineraryData InstrItins;
 
@@ -67,6 +100,7 @@ public:
   /// Only O32 and EABI supported right now.
   bool isABI_EABI() const { return MipsABI == EABI; }
   bool isABI_O32() const { return MipsABI == O32; }
+  unsigned getTargetABI() const { return MipsABI; }
 
   /// This constructor initializes the data members to match that
   /// of the specified module.
@@ -85,9 +119,19 @@ public:
   bool isGP32bit() const { return !IsGP64bit; };
   bool isSingleFloat() const { return IsSingleFloat; };
   bool isNotSingleFloat() const { return !IsSingleFloat; };
-  bool hasAllegrexVFPU() const { return HasAllegrexVFPU; };
-  bool isAllegrex() const { return IsAllegrex; };
-
+  bool hasVFPU() const { return HasVFPU; };
+  bool hasABICall() const { return HasABICall; };
+  bool hasAbsoluteCall() const { return HasAbsoluteCall; };
+  bool isLinux() const { return IsLinux; };
+  unsigned getSSectionThreshold() const { return SSectionThreshold; }
+
+  /// Features related to the presence of specific instructions.
+  bool hasSEInReg()   const { return HasSEInReg; };
+  bool hasCondMov()   const { return HasCondMov; };
+  bool hasMulDivAdd() const { return HasMulDivAdd; };
+  bool hasMinMax()    const { return HasMinMax; };
+  bool hasSwap()      const { return HasSwap; };
+  bool hasBitCount()  const { return HasBitCount; };
 };
 } // End llvm namespace