Fix cmake build, add TargetMachineRegistry.cpp that got restored in r75807

[oota-llvm.git] / lib / Target / PIC16 / PIC16ISelLowering.h

diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h
index b2a89db3ea83821948cfb510d48e6e586e542812..b40ea12c15f6a7849aab9218113c8076cbe5c1e4 100644 (file)
--- a/lib/Target/PIC16/PIC16ISelLowering.h
+++ b/lib/Target/PIC16/PIC16ISelLowering.h
@@ -19,6 +19,7 @@
 #include "PIC16Subtarget.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/Target/TargetLowering.h"
+#include <map>
 
 namespace llvm {
   namespace PIC16ISD {
@@ -37,15 +38,18 @@ namespace llvm {
       PIC16Store,
       PIC16StWF,
       Banksel,
-      MTLO,
-      MTHI,
+      MTLO,          // Move to low part of FSR
+      MTHI,          // Move to high part of FSR
+      MTPCLATH,      // Move to PCLATCH
+      PIC16Connect,  // General connector for PIC16 nodes
       BCF,
       LSLF,          // PIC16 Logical shift left
       LRLF,          // PIC16 Logical shift right
       RLF,           // Rotate left through carry
       RRF,           // Rotate right through carry
       CALL,          // PIC16 Call instruction 
-      SUBCC,        // Compare for equality or inequality.
+      CALLW,         // PIC16 CALLW instruction 
+      SUBCC,         // Compare for equality or inequality.
       SELECT_ICC,    // Psuedo to be caught in schedular and expanded to brcond.
       BRCOND,        // Conditional branch.
       Dummy
@@ -57,7 +61,7 @@ namespace llvm {
       ROM_SPACE = 1    // ROM address space number is 1
     };
     enum PIC16Libcall {
-      MUL_I8,
+      MUL_I8 = RTLIB::UNKNOWN_LIBCALL + 1,
       SRA_I8,
       SLL_I8,
       SRL_I8,
@@ -85,10 +89,25 @@ namespace llvm {
     SDValue LowerBinOp(SDValue Op, SelectionDAG &DAG);
     SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
     SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
-    SDValue LowerCallReturn(SDValue Op, SDValue Chain, SDValue FrameAddress,
-                            SDValue InFlag, SelectionDAG &DAG);
-    SDValue LowerCallArguments(SDValue Op, SDValue Chain, SDValue FrameAddress,
-                               SDValue InFlag, SelectionDAG &DAG);
+    // Call returns
+    SDValue 
+    LowerDirectCallReturn(SDValue Op, SDValue Chain, SDValue FrameAddress, 
+                          SDValue InFlag, SelectionDAG &DAG);
+    SDValue 
+    LowerIndirectCallReturn(SDValue Op, SDValue Chain, SDValue InFlag,
+                            SDValue DataAddr_Lo, SDValue DataAddr_Hi,
+                            SelectionDAG &DAG);
+
+    // Call arguments
+    SDValue 
+    LowerDirectCallArguments(SDValue Op, SDValue Chain, SDValue FrameAddress, 
+                             SDValue InFlag, SelectionDAG &DAG);
+
+    SDValue 
+    LowerIndirectCallArguments(SDValue Op, SDValue Chain, SDValue InFlag, 
+                               SDValue DataAddr_Lo, SDValue DataAddr_Hi, 
+                               SelectionDAG &DAG);
+
     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
     SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC,
@@ -115,6 +134,22 @@ namespace llvm {
     SDValue PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const; 
     SDValue PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const; 
 
+    // This function returns the Tmp Offset for FrameIndex. If any TmpOffset 
+    // already exists for the FI then it returns the same else it creates the 
+    // new offset and returns.
+    unsigned GetTmpOffsetForFI(unsigned FI, unsigned slot_size); 
+    void ResetTmpOffsetMap() { FiTmpOffsetMap.clear(); SetTmpSize(0); }
+    void InitReservedFrameCount(const Function *F); 
+
+    // Return the size of Tmp variable 
+    unsigned GetTmpSize() { return TmpSize; }
+    void SetTmpSize(unsigned Size) { TmpSize = Size; }
+
+    /// getFunctionAlignment - Return the Log2 alignment of this function.
+    virtual unsigned getFunctionAlignment(const Function *) const {
+      // FIXME: The function never seems to be aligned.
+      return 1;
+    }
   private:
     // If the Node is a BUILD_PAIR representing a direct Address,
     // then this function will return true.
@@ -139,6 +174,19 @@ namespace llvm {
     void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES, 
                             int &Offset);
 
+
+    // CALL node should have all legal operands only. Legalize all non-legal
+    // operands of CALL node and then return the new call will all operands
+    // legal.
+    SDValue LegalizeCALL(SDValue Op, SelectionDAG &DAG);
+
+    // For indirect calls data address of the callee frame need to be
+    // extracted. This function fills the arguments DataAddr_Lo and 
+    // DataAddr_Hi with the address of the callee frame.
+    void GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
+                        SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
+                        SelectionDAG &DAG); 
+
     // We can not have both operands of a binary operation in W.
     // This function is used to put one operand on stack and generate a load.
     SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl); 
@@ -168,6 +216,16 @@ namespace llvm {
     // Check if operation has a direct load operand.
     inline bool isDirectLoad(const SDValue Op);
 
+  private:
+    // The frameindexes generated for spill/reload are stack based.
+    // This maps maintain zero based indexes for these FIs.
+    std::map<unsigned, unsigned> FiTmpOffsetMap;
+    unsigned TmpSize;
+
+    // These are the frames for return value and argument passing 
+    // These FrameIndices will be expanded to foo.frame external symbol
+    // and all others will be expanded to foo.tmp external symbol.
+    unsigned ReservedFrameCount; 
   };
 } // namespace llvm