New feature: add support for target intrinsics being defined in the

[oota-llvm.git] / lib / Target / PIC16 / PIC16RegisterInfo.td

diff --git a/lib/Target/PIC16/PIC16RegisterInfo.td b/lib/Target/PIC16/PIC16RegisterInfo.td
index 21cc3e5810856966c6e1a27c83cd2dd2acc61b8b..938974f4d48ec2cc11b6f211ac8986fa0ea28d75 100644 (file)
--- a/lib/Target/PIC16/PIC16RegisterInfo.td
+++ b/lib/Target/PIC16/PIC16RegisterInfo.td
@@ -11,74 +11,22 @@
 //  Declarations that describe the PIC16 register file
 //===----------------------------------------------------------------------===//
 
-// We have banks of 32 registers each.
 class PIC16Reg<string n> : Register<n> {
-  field bits<5> Num;
   let Namespace = "PIC16";
 }
 
-// PIC16 CPU Registers
-class PIC16GPRReg<bits<5> num, string n> : PIC16Reg<n> {
-  let Num = num;
-}
-
-// CPU GPR Registers
-def FSR0 : PIC16GPRReg< 0, "FSR0">, DwarfRegNum<[0]>;
-def FSR1 : PIC16GPRReg< 1, "FSR1">, DwarfRegNum<[1]>;
+// PIC16 Registers.
+def W   : PIC16Reg<"W">;
+def FSR0   : PIC16Reg<"FSR0">;
+def FSR1   : PIC16Reg<"FSR1">;
+def BS     : PIC16Reg<"BS">;
 
-// CPU Registers Class
-def PTRRegs : RegisterClass<"PIC16", [i16], 8, 
-  [FSR0, FSR1]>
-{
-  let MethodProtos = [{
-    iterator allocation_order_end(const MachineFunction &MF) const;
-  }];
-  let MethodBodies = [{
-    PTRRegsClass::iterator
-    PTRRegsClass::allocation_order_end(const MachineFunction &MF) const {
-      return end();
-    }
-  }];
-}
+def STATUS : PIC16Reg<"STATUS">;
 
-def WREG : PIC16GPRReg< 0, "WREG">, DwarfRegNum<[0]>;
-
-// CPU Registers Class
-def CPURegs : RegisterClass<"PIC16", [i8], 8, 
-  [WREG]>
-{
-  let MethodProtos = [{
-    iterator allocation_order_end(const MachineFunction &MF) const;
-  }];
-  let MethodBodies = [{
-    CPURegsClass::iterator
-    CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
-      return end();
-    }
-  }];
-}
+// PIC16 Register classes.
+def GPR    : RegisterClass<"PIC16", [i8], 8, [W]>;
+def FSR16  : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]>;
+def BSR  : RegisterClass<"PIC16", [i8], 8, [BS]>;
 
-def STATUSREG : PIC16GPRReg<2, "STATUS">, DwarfRegNum<[0]>;
+def STATUSR: RegisterClass<"PIC16", [i8], 8, [STATUS]>;
 
-// STATUS Registers Class
-def STATUSRegs : RegisterClass<"PIC16", [i8], 8, 
-  [STATUSREG]>;
-
-
-// Dummy stack pointer.
-def STKPTR : PIC16GPRReg< 0, "SP">, DwarfRegNum<[0]>;
-
-// CPU Registers Class
-def STKRegs : RegisterClass<"PIC16", [i8], 8, 
-  [STKPTR]>
-{
-  let MethodProtos = [{
-    iterator allocation_order_end(const MachineFunction &MF) const;
-  }];
-  let MethodBodies = [{
-    STKRegsClass::iterator
-    STKRegsClass::allocation_order_end(const MachineFunction &MF) const {
-      return end();
-    }
-  }];
-}