RISC architectures get their memory operand folding for free.

[oota-llvm.git] / lib / Target / PowerPC / Makefile

diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile
index f210964b8cb94e557b1c38d4a637485eb3923372..1265f1d36910bc563d996d122cf48a8b45f45c58 100644 (file)
--- a/lib/Target/PowerPC/Makefile
+++ b/lib/Target/PowerPC/Makefile
@@ -1,53 +1,23 @@
 ##===- lib/Target/PowerPC/Makefile -------------------------*- Makefile -*-===##
-# 
+#
 #                     The LLVM Compiler Infrastructure
 #
-# This file was developed by the LLVM research group and is distributed under
-# the University of Illinois Open Source License. See LICENSE.TXT for details.
-# 
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
 ##===----------------------------------------------------------------------===##
-LEVEL = ../../..
-LIBRARYNAME = powerpc
-include $(LEVEL)/Makefile.common
 
-TARGET = PowerPC
+LEVEL = ../../..
+LIBRARYNAME = LLVMPowerPCCodeGen
+TARGET = PPC
 
 # Make sure that tblgen is run, first thing.
-$(SourceDepend): PowerPCGenRegisterInfo.h.inc PowerPCGenRegisterNames.inc \
-                 PowerPCGenRegisterInfo.inc PowerPCGenInstrNames.inc \
-                 PowerPCGenInstrInfo.inc PowerPCGenCodeEmitter.inc \
-                 PowerPCGenAsmWriter.inc
-
-TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
-          $(SourceDir)/../Target.td
-
-$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
-       @echo "Building $(TARGET).td register names with tblgen"
-       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
+BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
+                PPCGenAsmWriter.inc  PPCGenCodeEmitter.inc \
+                PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
+                PPCGenInstrInfo.inc PPCGenDAGISel.inc \
+                PPCGenSubtarget.inc PPCGenCallingConv.inc
 
-$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
-       @echo "Building $(TARGET).td register information header with tblgen"
-       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
+DIRS = AsmPrinter TargetInfo
 
-$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
-       @echo "Building $(TARGET).td register information implementation with tblgen"
-       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
-
-$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
-       @echo "Building $(TARGET).td instruction names with tblgen"
-       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
-
-$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
-       @echo "Building $(TARGET).td instruction information with tblgen"
-       $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-
-$(TARGET)GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN)
-       @echo "Building $(TARGET).td code emitter"
-       $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
-
-$(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN)
-       @echo "Building $(TARGET).td assembly writer with tblgen"
-       $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@
-
-clean::
-       $(VERB) rm -f *.inc
+include $(LEVEL)/Makefile.common