RISC architectures get their memory operand folding for free.

[oota-llvm.git] / lib / Target / PowerPC / PPC.td

diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index 76f8ac4806053aace23828a81699972882a61b25..27644b2daca872fbee099808ed1fdccda28407ba 100644 (file)
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -13,7 +13,7 @@
 
 // Get the target-independent interfaces which we are implementing.
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // PowerPC Subtarget features.
@@ -96,14 +96,6 @@ def : Processor<"ppc64", G5Itineraries,
 include "PPCCallingConv.td"
 
 def PPCInstrInfo : InstrInfo {
-  // Define how we want to layout our TargetSpecific information field... This
-  // should be kept up-to-date with the fields in the PPCInstrInfo.h file.
-  let TSFlagsFields = ["PPC970_First",
-                       "PPC970_Single",
-                       "PPC970_Cracked",
-                       "PPC970_Unit"];
-  let TSFlagsShifts = [0, 1, 2, 3];
-
   let isLittleEndianEncoding = 1;
 }