The BLX instruction is encoded differently than the BL, because why not? In

[oota-llvm.git] / lib / Target / PowerPC / PPC.td

diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index 93edd0dc348622fde3a88f41a95c7de8862de92f..aabf494012e25dc4fc271ffe6f55b380f0d7b5b9 100644 (file)
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -13,22 +13,39 @@
 
 // Get the target-independent interfaces which we are implementing.
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // PowerPC Subtarget features.
 //
  
-def Feature64Bit     : SubtargetFeature<"64bit",
+//===----------------------------------------------------------------------===//
+// CPU Directives                                                             //
+//===----------------------------------------------------------------------===//
+
+def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
+def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
+def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
+def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
+def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
+def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
+def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
+def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
+def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
+def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
+
+def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
                                         "Enable 64-bit instructions">;
-def Feature64BitRegs : SubtargetFeature<"64bitregs",
-                                        "Enable 64-bit registers [beta]">;
-def FeatureAltivec   : SubtargetFeature<"altivec",
+def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
+                              "Enable 64-bit registers usage for ppc32 [beta]">;
+def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
                                         "Enable Altivec instructions">;
-def FeatureGPUL      : SubtargetFeature<"gpul",
+def FeatureGPUL      : SubtargetFeature<"gpul","IsGigaProcessor", "true",
                                         "Enable GPUL instructions">;
-def FeatureFSqrt     : SubtargetFeature<"fsqrt",
+def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
                                         "Enable the fsqrt instruction">; 
+def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
+                                        "Enable the stfiwx instruction">; 
 
 //===----------------------------------------------------------------------===//
 // Register File Description
@@ -42,40 +59,54 @@ include "PPCInstrInfo.td"
 // PowerPC processors supported.
 //
 
-def : Processor<"generic", G3Itineraries, []>;
-def : Processor<"601", G3Itineraries, []>;
-def : Processor<"602", G3Itineraries, []>;
-def : Processor<"603", G3Itineraries, []>;
-def : Processor<"603e", G3Itineraries, []>;
-def : Processor<"603ev", G3Itineraries, []>;
-def : Processor<"604", G3Itineraries, []>;
-def : Processor<"604e", G3Itineraries, []>;
-def : Processor<"620", G3Itineraries, []>;
-def : Processor<"g3", G3Itineraries, []>;
-def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
-def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
-def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
-def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
-def : Processor<"750", G3Itineraries, []>;
+def : Processor<"generic", G3Itineraries, [Directive32]>;
+def : Processor<"601", G3Itineraries, [Directive601]>;
+def : Processor<"602", G3Itineraries, [Directive602]>;
+def : Processor<"603", G3Itineraries, [Directive603]>;
+def : Processor<"603e", G3Itineraries, [Directive603]>;
+def : Processor<"603ev", G3Itineraries, [Directive603]>;
+def : Processor<"604", G3Itineraries, [Directive604]>;
+def : Processor<"604e", G3Itineraries, [Directive604]>;
+def : Processor<"620", G3Itineraries, [Directive620]>;
+def : Processor<"g3", G3Itineraries, [Directive7400]>;
+def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
+def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
+def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
+def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
+def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
 def : Processor<"970", G5Itineraries,
-                  [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+                  [Directive970, FeatureAltivec,
+                   FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
                    Feature64Bit /*, Feature64BitRegs */]>;
 def : Processor<"g5", G5Itineraries,
-                  [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+                  [Directive970, FeatureAltivec,
+                   FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
+                   Feature64Bit /*, Feature64BitRegs */]>;
+def : Processor<"ppc", G3Itineraries, [Directive32]>;
+def : Processor<"ppc64", G5Itineraries,
+                  [Directive64, FeatureAltivec,
+                   FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
                    Feature64Bit /*, Feature64BitRegs */]>;
 
 
-def PPC : Target {
-  // Pointers on PPC are 32-bits in size.
-  let PointerType = i32;
+//===----------------------------------------------------------------------===//
+// Calling Conventions
+//===----------------------------------------------------------------------===//
+
+include "PPCCallingConv.td"
+
+def PPCInstrInfo : InstrInfo {
+  let isLittleEndianEncoding = 1;
+}
 
-  // According to the Mach-O Runtime ABI, these regs are nonvolatile across
-  // calls
-  let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
-    R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
-    F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
-    F30, F31, CR2, CR3, CR4, LR];
+def PPCAsmWriter : AsmWriter {
+  string AsmWriterClassName  = "InstPrinter";
+  bit isMCAsmWriter = 1;
+}
 
-  // Pull in Instruction Info:
-  let InstructionSet = PowerPCInstrInfo;
+def PPC : Target {
+  // Information about the instructions.
+  let InstructionSet = PPCInstrInfo;
+  
+  let AssemblyWriters = [PPCAsmWriter];
 }