-//===-- PowerPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
+//===-- PPC32AsmPrinter.cpp - Print machine instrs to PowerPC assembly ----===//
//
// The LLVM Compiler Infrastructure
//
#define DEBUG_TYPE "asmprinter"
#include "PowerPC.h"
#include "PowerPCInstrInfo.h"
-#include "PowerPCTargetMachine.h"
+#include "PPC32TargetMachine.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Module.h"
/// Target machine description which we query for reg. names, data
/// layout, etc.
///
- PowerPCTargetMachine &TM;
+ PPC32TargetMachine &TM;
/// Name-mangler for global names.
///
std::set<std::string> Strings;
Printer(std::ostream &o, TargetMachine &tm) : O(o),
- TM(reinterpret_cast<PowerPCTargetMachine&>(tm)), LabelNumber(0) {}
+ TM(reinterpret_cast<PPC32TargetMachine&>(tm)), LabelNumber(0) {}
/// Cache of mangled name for current function. This is
/// recalculated at the beginning of each call to
unsigned LabelNumber;
virtual const char *getPassName() const {
- return "PowerPC Assembly Printer";
+ return "PPC32 Assembly Printer";
}
void printMachineInstruction(const MachineInstr *MI);
};
} // end of anonymous namespace
-/// createPPCAsmPrinterPass - Returns a pass that prints the PPC
+/// createPPC32AsmPrinterPass - Returns a pass that prints the PPC
/// assembly code for a MachineFunction to the given output stream,
/// using the given target machine description. This should work
/// regardless of whether the function is in SSA form or not.
///
-FunctionPass *createPPCAsmPrinterPass(std::ostream &o,TargetMachine &tm) {
+FunctionPass *createPPC32AsmPrinter(std::ostream &o,TargetMachine &tm) {
return new Printer(o, tm);
}
void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
int Imm = MO.getImmedValue();
- if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
+ if (ArgType == PPCII::Simm16 || ArgType == PPCII::Disimm16) {
O << (short)Imm;
- } else if (ArgType == PPC32II::Zimm16) {
+ } else if (ArgType == PPCII::Zimm16) {
O << (unsigned short)Imm;
} else {
O << Imm;
}
}
-/// printMachineInstruction -- Print out a single PPC32 LLVM instruction
+/// printMachineInstruction -- Print out a single PPC LLVM instruction
/// MI in Darwin syntax to the current output stream.
///
void Printer::printMachineInstruction(const MachineInstr *MI) {
unsigned ArgCount = MI->getNumOperands();
unsigned ArgType[] = {
- (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
- (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
- (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
- (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask,
- (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask
+ (Desc.TSFlags >> PPCII::Arg0TypeShift) & PPCII::ArgTypeMask,
+ (Desc.TSFlags >> PPCII::Arg1TypeShift) & PPCII::ArgTypeMask,
+ (Desc.TSFlags >> PPCII::Arg2TypeShift) & PPCII::ArgTypeMask,
+ (Desc.TSFlags >> PPCII::Arg3TypeShift) & PPCII::ArgTypeMask,
+ (Desc.TSFlags >> PPCII::Arg4TypeShift) & PPCII::ArgTypeMask
};
- assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
+ assert(((Desc.TSFlags & PPCII::VMX) == 0) &&
"Instruction requires VMX support");
- assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
+ assert(((Desc.TSFlags & PPCII::PPC64) == 0) &&
"Instruction requires 64 bit support");
++EmittedInsts;
// appropriate number of args that the assembler expects. This is because
// may have many arguments appended to record the uses of registers that are
// holding arguments to the called function.
- if (Opcode == PPC32::COND_BRANCH) {
+ if (Opcode == PPC::COND_BRANCH) {
std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
abort();
- } else if (Opcode == PPC32::IMPLICIT_DEF) {
+ } else if (Opcode == PPC::IMPLICIT_DEF) {
O << "; IMPLICIT DEF ";
printOp(MI->getOperand(0));
O << "\n";
return;
- } else if (Opcode == PPC32::CALLpcrel) {
+ } else if (Opcode == PPC::CALLpcrel) {
O << TII.getName(Opcode) << " ";
printOp(MI->getOperand(0));
O << "\n";
return;
- } else if (Opcode == PPC32::CALLindirect) {
+ } else if (Opcode == PPC::CALLindirect) {
O << TII.getName(Opcode) << " ";
printImmOp(MI->getOperand(0), ArgType[0]);
O << ", ";
printImmOp(MI->getOperand(1), ArgType[0]);
O << "\n";
return;
- } else if (Opcode == PPC32::MovePCtoLR) {
+ } else if (Opcode == PPC::MovePCtoLR) {
// FIXME: should probably be converted to cout.width and cout.fill
O << "bl \"L0000" << LabelNumber << "$pb\"\n";
O << "\"L0000" << LabelNumber << "$pb\":\n";
}
O << TII.getName(Opcode) << " ";
- if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
+ if (Opcode == PPC::LOADLoDirect || Opcode == PPC::LOADLoIndirect) {
printOp(MI->getOperand(0));
O << ", lo16(";
printOp(MI->getOperand(2));
O << "-\"L0000" << LabelNumber << "$pb\")";
O << "(";
- if (MI->getOperand(1).getReg() == PPC32::R0)
+ if (MI->getOperand(1).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(1));
O << ")\n";
- } else if (Opcode == PPC32::LOADHiAddr) {
+ } else if (Opcode == PPC::LOADHiAddr) {
printOp(MI->getOperand(0));
O << ", ";
- if (MI->getOperand(1).getReg() == PPC32::R0)
+ if (MI->getOperand(1).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(1));
O << ", ha16(" ;
printOp(MI->getOperand(2));
O << "-\"L0000" << LabelNumber << "$pb\")\n";
- } else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
+ } else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) {
printOp(MI->getOperand(0));
O << ", ";
printImmOp(MI->getOperand(1), ArgType[1]);
O << "(";
if (MI->getOperand(2).hasAllocatedReg() &&
- MI->getOperand(2).getReg() == PPC32::R0)
+ MI->getOperand(2).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(2));
} else {
for (i = 0; i < ArgCount; ++i) {
// addi and friends
- if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 &&
+ if (i == 1 && ArgCount == 3 && ArgType[2] == PPCII::Simm16 &&
MI->getOperand(1).hasAllocatedReg() &&
- MI->getOperand(1).getReg() == PPC32::R0) {
+ MI->getOperand(1).getReg() == PPC::R0) {
O << "0";
// for long branch support, bc $+8
} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&