//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Nate Baegeman and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "PPCPredicates.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;
STATISTIC(NumExpanded, "Number of branches expanded to long format");
namespace {
- struct VISIBILITY_HIDDEN PPCBSel : public MachineFunctionPass {
+ struct PPCBSel : public MachineFunctionPass {
+ static char ID;
+ PPCBSel() : MachineFunctionPass(&ID) {}
+
/// BlockSizes - The sizes of the basic blocks in the function.
std::vector<unsigned> BlockSizes;
return "PowerPC Branch Selector";
}
};
+ char PPCBSel::ID = 0;
}
/// createPPCBranchSelectionPass - returns an instance of the Branch Selection
return new PPCBSel();
}
-/// getNumBytesForInstruction - Return the number of bytes of code the specified
-/// instruction may be. This returns the maximum number of bytes.
-///
-static unsigned getNumBytesForInstruction(MachineInstr *MI) {
- switch (MI->getOpcode()) {
- case PPC::IMPLICIT_DEF_GPRC: // no asm emitted
- case PPC::IMPLICIT_DEF_G8RC: // no asm emitted
- case PPC::IMPLICIT_DEF_F4: // no asm emitted
- case PPC::IMPLICIT_DEF_F8: // no asm emitted
- case PPC::IMPLICIT_DEF_VRRC: // no asm emitted
- return 0;
- case PPC::INLINEASM: { // Inline Asm: Variable size.
- MachineFunction *MF = MI->getParent()->getParent();
- const char *AsmStr = MI->getOperand(0).getSymbolName();
- return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
- }
- case PPC::LABEL: {
- return 0;
- }
- default:
- return 4; // PowerPC instructions are all 4 bytes
- }
-}
-
-
bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
// Give the blocks of the function a dense, in-order, numbering.
unsigned BlockSize = 0;
for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
MBBI != EE; ++MBBI)
- BlockSize += getNumBytesForInstruction(MBBI);
+ BlockSize += TII->GetInstSizeInBytes(MBBI);
BlockSizes[MBB->getNumber()] = BlockSize;
FuncSize += BlockSize;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) {
- MBBStartOffset += getNumBytesForInstruction(I);
+ MBBStartOffset += TII->GetInstSizeInBytes(I);
continue;
}
// Determine the offset from the current branch to the destination
// block.
- MachineBasicBlock *Dest = I->getOperand(2).getMachineBasicBlock();
+ MachineBasicBlock *Dest = I->getOperand(2).getMBB();
int BranchSize;
if (Dest->getNumber() <= MBB.getNumber()) {
unsigned CRReg = I->getOperand(1).getReg();
MachineInstr *OldBranch = I;
+ DebugLoc dl = OldBranch->getDebugLoc();
// Jump over the uncond branch inst (i.e. $PC+8) on opposite condition.
- BuildMI(MBB, I, TII->get(PPC::BCC))
+ BuildMI(MBB, I, dl, TII->get(PPC::BCC))
.addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
// Uncond branch to the real destination.
- I = BuildMI(MBB, I, TII->get(PPC::B)).addMBB(Dest);
+ I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
// Remove the old branch from the function.
OldBranch->eraseFromParent();