//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
-// JIT-compile bytecode to native PowerPC.
+// JIT-compile bitcode to native PowerPC.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineCodeEmitter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
///
- int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
+ unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO);
+
+ void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<MachineModuleInfo>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
public:
+ static char ID;
PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
- : TM(T), MCE(M) {}
+ : MachineFunctionPass(&ID), TM(T), MCE(M) {}
const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
///
- unsigned getBinaryCodeForInstr(MachineInstr &MI);
+ unsigned getBinaryCodeForInstr(const MachineInstr &MI);
};
+ char PPCCodeEmitter::ID = 0;
}
/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
return new PPCCodeEmitter(TM, MCE);
}
-#ifdef __APPLE__
-extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
-#endif
-
bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
MF.getTarget().getRelocationModel() != Reloc::Static) &&
"JIT relocation model must be set to static or default!");
+
+ MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
do {
MovePCtoLROffset = 0;
MCE.startFunction(MF);
MCE.StartMachineBasicBlock(&MBB);
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
- MachineInstr &MI = *I;
+ const MachineInstr &MI = *I;
switch (MI.getOpcode()) {
default:
- MCE.emitWordBE(getBinaryCodeForInstr(*I));
+ MCE.emitWordBE(getBinaryCodeForInstr(MI));
break;
- case PPC::IMPLICIT_DEF_GPRC:
- case PPC::IMPLICIT_DEF_G8RC:
- case PPC::IMPLICIT_DEF_F8:
- case PPC::IMPLICIT_DEF_F4:
- case PPC::IMPLICIT_DEF_VRRC:
+ case TargetInstrInfo::DBG_LABEL:
+ case TargetInstrInfo::EH_LABEL:
+ MCE.emitLabel(MI.getOperand(0).getImm());
+ break;
+ case TargetInstrInfo::IMPLICIT_DEF:
break; // pseudo opcode, no side effects
case PPC::MovePCtoLR:
case PPC::MovePCtoLR8:
}
}
-int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
+unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO) {
- intptr_t rv = 0; // Return value; defaults to 0 for unhandled cases
+ unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
- if (MO.isRegister()) {
+ if (MO.isReg()) {
rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());
// Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
rv = 0x80 >> rv;
}
- } else if (MO.isImmediate()) {
- rv = MO.getImmedValue();
- } else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
- MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
+ } else if (MO.isImm()) {
+ rv = MO.getImm();
+ } else if (MO.isGlobal() || MO.isSymbol() ||
+ MO.isCPI() || MO.isJTI()) {
unsigned Reloc = 0;
- if (MI.getOpcode() == PPC::BL || MI.getOpcode() == PPC::BL8)
+ if (MI.getOpcode() == PPC::BL_Macho || MI.getOpcode() == PPC::BL8_Macho ||
+ MI.getOpcode() == PPC::BL_ELF || MI.getOpcode() == PPC::BL8_ELF ||
+ MI.getOpcode() == PPC::TAILB || MI.getOpcode() == PPC::TAILB8)
Reloc = PPC::reloc_pcrel_bx;
else {
- // If in PIC mode, we need to encode the negated address of the
- // 'movepctolr' into the unrelocated field. After relocation, we'll have
- // &gv-&movepctolr in the imm field. Once &movepctolr is added to the imm
- // field, we get &gv.
if (TM.getRelocationModel() == Reloc::PIC_) {
assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
- rv = -(intptr_t)MovePCtoLROffset - 4;
}
-
switch (MI.getOpcode()) {
default: MI.dump(); assert(0 && "Unknown instruction for relocation!");
case PPC::LIS:
case PPC::ADDIS:
case PPC::ADDIS8:
Reloc = PPC::reloc_absolute_high; // Pointer to symbol
- rv >>= 16;
break;
case PPC::LI:
case PPC::LI8:
case PPC::LA:
// Loads.
case PPC::LBZ:
+ case PPC::LBZ8:
case PPC::LHA:
+ case PPC::LHA8:
case PPC::LHZ:
+ case PPC::LHZ8:
case PPC::LWZ:
+ case PPC::LWZ8:
case PPC::LFS:
case PPC::LFD:
- case PPC::LWZ8:
// Stores.
case PPC::STB:
+ case PPC::STB8:
case PPC::STH:
+ case PPC::STH8:
case PPC::STW:
+ case PPC::STW8:
case PPC::STFS:
case PPC::STFD:
Reloc = PPC::reloc_absolute_low;
- rv &= 0xFFFF;
break;
case PPC::LWA:
case PPC::STD:
case PPC::STD_32:
Reloc = PPC::reloc_absolute_low_ix;
- rv &= 0xFFFF;
- rv >>= 2;
break;
}
}
- if (MO.isGlobalAddress())
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
- Reloc, MO.getGlobal(), 0));
- else if (MO.isExternalSymbol())
- MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
- Reloc, MO.getSymbolName(), 0));
- else if (MO.isConstantPoolIndex())
- MCE.addRelocation(MachineRelocation::getConstPool(
- MCE.getCurrentPCOffset(),
- Reloc, MO.getConstantPoolIndex(), 0));
- else // isJumpTableIndex
- MCE.addRelocation(MachineRelocation::getJumpTable(
- MCE.getCurrentPCOffset(),
- Reloc, MO.getJumpTableIndex(), 0));
- } else if (MO.isMachineBasicBlock()) {
+
+ MachineRelocation R;
+ if (MO.isGlobal()) {
+ R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
+ MO.getGlobal(), 0,
+ isa<Function>(MO.getGlobal()));
+ } else if (MO.isSymbol()) {
+ R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
+ Reloc, MO.getSymbolName(), 0);
+ } else if (MO.isCPI()) {
+ R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
+ Reloc, MO.getIndex(), 0);
+ } else {
+ assert(MO.isJTI());
+ R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
+ Reloc, MO.getIndex(), 0);
+ }
+
+ // If in PIC mode, we need to encode the negated address of the
+ // 'movepctolr' into the unrelocated field. After relocation, we'll have
+ // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
+ // field, we get &gv. This doesn't happen for branch relocations, which are
+ // always implicitly pc relative.
+ if (TM.getRelocationModel() == Reloc::PIC_ && Reloc != PPC::reloc_pcrel_bx){
+ assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
+ R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4);
+ }
+ MCE.addRelocation(R);
+
+ } else if (MO.isMBB()) {
unsigned Reloc = 0;
unsigned Opcode = MI.getOpcode();
- if (Opcode == PPC::B || Opcode == PPC::BL || Opcode == PPC::BLA)
+ if (Opcode == PPC::B || Opcode == PPC::BL_Macho ||
+ Opcode == PPC::BLA_Macho || Opcode == PPC::BL_ELF ||
+ Opcode == PPC::BLA_ELF)
Reloc = PPC::reloc_pcrel_bx;
else // BCC instruction
Reloc = PPC::reloc_pcrel_bcx;
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
- Reloc,
- MO.getMachineBasicBlock()));
+ Reloc, MO.getMBB()));
} else {
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
abort();