//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Chris Lattner and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "sched"
+#define DEBUG_TYPE "pre-RA-sched"
#include "PPCHazardRecognizers.h"
#include "PPC.h"
#include "PPCInstrInfo.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/Debug.h"
-#include <iostream>
using namespace llvm;
-
//===----------------------------------------------------------------------===//
// PowerPC 970 Hazard Recognizer
//
//
// FIXME: This is missing some significant cases:
// 1. Modeling of microcoded instructions.
-// 2. Handling of cracked instructions.
-// 3. Handling of serialized operations.
-// 4. Handling of the esoteric cases in "Resource-based Instruction Grouping",
-// e.g. integer divides that only execute in the second slot.
+// 2. Handling of serialized operations.
+// 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
//
PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
}
void PPCHazardRecognizer970::EndDispatchGroup() {
- DEBUG(std::cerr << "=== Start of dispatch group\n");
+ DOUT << "=== Start of dispatch group\n";
NumIssued = 0;
// Structural hazard info.
PPCII::PPC970_Unit
PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
bool &isFirst, bool &isSingle,
- bool &isLoad, bool &isStore){
- if (Opcode < ISD::BUILTIN_OP_END) {
- isFirst = isSingle = isLoad = isStore = false;
+ bool &isCracked,
+ bool &isLoad, bool &isStore) {
+ if ((int)Opcode >= 0) {
+ isFirst = isSingle = isCracked = isLoad = isStore = false;
return PPCII::PPC970_Pseudo;
}
- Opcode -= ISD::BUILTIN_OP_END;
+ Opcode = ~Opcode;
- const TargetInstrDescriptor &TID = TII.get(Opcode);
+ const TargetInstrDesc &TID = TII.get(Opcode);
- isLoad = TID.Flags & M_LOAD_FLAG;
- isStore = TID.Flags & M_STORE_FLAG;
+ isLoad = TID.mayLoad();
+ isStore = TID.mayStore();
unsigned TSFlags = TID.TSFlags;
- isFirst = TSFlags & PPCII::PPC970_First;
- isSingle = TSFlags & PPCII::PPC970_Single;
+ isFirst = TSFlags & PPCII::PPC970_First;
+ isSingle = TSFlags & PPCII::PPC970_Single;
+ isCracked = TSFlags & PPCII::PPC970_Cracked;
return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
}
/// isLoadOfStoredAddress - If we have a load from the previously stored pointer
/// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
bool PPCHazardRecognizer970::
-isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
+isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const {
for (unsigned i = 0, e = NumStores; i != e; ++i) {
// Handle exact and commuted addresses.
if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
// Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
// to see if the load and store actually overlap.
- int StoreOffs = StoreOffset->getValue();
- int LoadOffs = LoadOffset->getValue();
+ int StoreOffs = StoreOffset->getZExtValue();
+ int LoadOffs = LoadOffset->getZExtValue();
if (StoreOffs < LoadOffs) {
- if (int(StoreOffs+StoreSize) > LoadOffs) return true;
+ if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true;
} else {
if (int(LoadOffs+LoadSize) > StoreOffs) return true;
}
/// terminate terminate the dispatch group. We turn NoopHazard for any
/// instructions that wouldn't terminate the dispatch group that would cause a
/// pipeline flush.
-HazardRecognizer::HazardType PPCHazardRecognizer970::
-getHazardType(SDNode *Node) {
- bool isFirst, isSingle, isLoad, isStore;
+ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
+getHazardType(SUnit *SU) {
+ const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
+ bool isFirst, isSingle, isCracked, isLoad, isStore;
PPCII::PPC970_Unit InstrType =
- GetInstrType(Node->getOpcode(), isFirst, isSingle, isLoad, isStore);
+ GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
+ isLoad, isStore);
if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
- unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
+ unsigned Opcode = Node->getMachineOpcode();
// We can only issue a PPC970_First/PPC970_Single instruction (such as
// crand/mtspr/etc) if this is the first cycle of the dispatch group.
- if (NumIssued != 0 && (isFirst || isSingle) )
+ if (NumIssued != 0 && (isFirst || isSingle))
return Hazard;
+ // If this instruction is cracked into two ops by the decoder, we know that
+ // it is not a branch and that it cannot issue if 3 other instructions are
+ // already in the dispatch group.
+ if (isCracked && NumIssued > 2)
+ return Hazard;
+
switch (InstrType) {
default: assert(0 && "Unknown instruction type!");
case PPCII::PPC970_FXU:
case PPCII::PPC970_BRU:
break;
}
-
+
// Do not allow MTCTR and BCTRL to be in the same dispatch group.
- if (HasCTRSet && Opcode == PPC::BCTRL)
+ if (HasCTRSet && (Opcode == PPC::BCTRL_Macho || Opcode == PPC::BCTRL_ELF))
return NoopHazard;
// If this is a load following a store, make sure it's not to the same or
// overlapping address.
- if (isLoad && StoreSize) {
+ if (isLoad && NumStores) {
unsigned LoadSize;
switch (Opcode) {
default: assert(0 && "Unknown load!");
- case PPC::LBZ:
+ case PPC::LBZ: case PPC::LBZU:
case PPC::LBZX:
+ case PPC::LBZ8: case PPC::LBZU8:
+ case PPC::LBZX8:
case PPC::LVEBX:
LoadSize = 1;
break;
- case PPC::LHA:
+ case PPC::LHA: case PPC::LHAU:
case PPC::LHAX:
- case PPC::LHZ:
+ case PPC::LHZ: case PPC::LHZU:
case PPC::LHZX:
case PPC::LVEHX:
+ case PPC::LHBRX:
+ case PPC::LHA8: case PPC::LHAU8:
+ case PPC::LHAX8:
+ case PPC::LHZ8: case PPC::LHZU8:
+ case PPC::LHZX8:
LoadSize = 2;
break;
- case PPC::LFS:
+ case PPC::LFS: case PPC::LFSU:
case PPC::LFSX:
- case PPC::LWZ:
+ case PPC::LWZ: case PPC::LWZU:
case PPC::LWZX:
- case PPC::LWZU:
case PPC::LWA:
case PPC::LWAX:
case PPC::LVEWX:
+ case PPC::LWBRX:
+ case PPC::LWZ8:
+ case PPC::LWZX8:
LoadSize = 4;
break;
- case PPC::LFD:
+ case PPC::LFD: case PPC::LFDU:
case PPC::LFDX:
- case PPC::LD:
+ case PPC::LD: case PPC::LDU:
case PPC::LDX:
LoadSize = 8;
break;
case PPC::LVX:
+ case PPC::LVXL:
LoadSize = 16;
break;
}
return NoHazard;
}
-void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
- bool isFirst, isSingle, isLoad, isStore;
+void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
+ const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
+ bool isFirst, isSingle, isCracked, isLoad, isStore;
PPCII::PPC970_Unit InstrType =
- GetInstrType(Node->getOpcode(), isFirst, isSingle, isLoad, isStore);
+ GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
+ isLoad, isStore);
if (InstrType == PPCII::PPC970_Pseudo) return;
- unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
+ unsigned Opcode = Node->getMachineOpcode();
// Update structural hazard information.
if (Opcode == PPC::MTCTR) HasCTRSet = true;
unsigned ThisStoreSize;
switch (Opcode) {
default: assert(0 && "Unknown store instruction!");
- case PPC::STBX:
- case PPC::STB:
+ case PPC::STB: case PPC::STB8:
+ case PPC::STBU: case PPC::STBU8:
+ case PPC::STBX: case PPC::STBX8:
case PPC::STVEBX:
ThisStoreSize = 1;
break;
- case PPC::STHX:
- case PPC::STH:
+ case PPC::STH: case PPC::STH8:
+ case PPC::STHU: case PPC::STHU8:
+ case PPC::STHX: case PPC::STHX8:
case PPC::STVEHX:
+ case PPC::STHBRX:
ThisStoreSize = 2;
break;
case PPC::STFS:
+ case PPC::STFSU:
case PPC::STFSX:
- case PPC::STWU:
- case PPC::STWX:
+ case PPC::STWX: case PPC::STWX8:
case PPC::STWUX:
- case PPC::STW:
+ case PPC::STW: case PPC::STW8:
+ case PPC::STWU: case PPC::STWU8:
case PPC::STVEWX:
case PPC::STFIWX:
+ case PPC::STWBRX:
ThisStoreSize = 4;
break;
+ case PPC::STD_32:
+ case PPC::STDX_32:
case PPC::STD:
case PPC::STDU:
case PPC::STFD:
ThisStoreSize = 8;
break;
case PPC::STVX:
+ case PPC::STVXL:
ThisStoreSize = 16;
break;
}
NumIssued = 4; // Terminate a d-group.
++NumIssued;
+ // If this instruction is cracked into two ops by the decoder, remember that
+ // we issued two pieces.
+ if (isCracked)
+ ++NumIssued;
+
if (NumIssued == 5)
EndDispatchGroup();
}
if (NumIssued == 5)
EndDispatchGroup();
}
-
-void PPCHazardRecognizer970::EmitNoop() {
- AdvanceCycle();
-}
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