#include "PowerPC.h"
#include "PPC32TargetMachine.h"
#include "PPC32ISelLowering.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/Constants.h"
+#include "llvm/GlobalValue.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;
namespace {
- Statistic<> Recorded("ppc-codegen", "Number of recording ops emitted");
Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
///
class PPC32DAGToDAGISel : public SelectionDAGISel {
PPC32TargetLowering PPC32Lowering;
-
unsigned GlobalBaseReg;
- bool GlobalBaseInitialized;
public:
PPC32DAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
- /// runOnFunction - Override this function in order to reset our
- /// per-function variables.
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
- GlobalBaseInitialized = false;
+ GlobalBaseReg = 0;
return SelectionDAGISel::runOnFunction(Fn);
}
-
+
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDOperand getI32Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
+
+ /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
+ /// base register. Return the virtual register that holds this value.
+ SDOperand getGlobalBaseReg();
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
unsigned OCHi, unsigned OCLo,
bool IsArithmetic = false,
bool Negate = false);
-
+ SDNode *SelectBitfieldInsert(SDNode *N);
+
+ /// SelectCC - Select a comparison of the specified values with the
+ /// specified condition code, returning the CR# of the expression.
+ SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
+
+ /// SelectAddr - Given the specified address, return the two operands for a
+ /// load/store instruction, and return true if it should be an indexed [r+r]
+ /// operation.
+ bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
+
/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
DEBUG(BB->dump());
- // Codegen the basic block.
+ // Select target instructions for the DAG.
Select(DAG.getRoot());
DAG.RemoveDeadNodes();
- DAG.viewGraph();
+
+ // Emit machine code to BB.
+ ScheduleAndEmitDAG(DAG);
}
virtual const char *getPassName() const {
};
}
+/// getGlobalBaseReg - Output the instructions required to put the
+/// base address to use for accessing globals into a register.
+///
+SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
+ if (!GlobalBaseReg) {
+ // Insert the set of GlobalBaseReg into the first MBB of the function
+ MachineBasicBlock &FirstMBB = BB->getParent()->front();
+ MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+ SSARegMap *RegMap = BB->getParent()->getSSARegMap();
+ GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
+ BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
+ BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
+ }
+ return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
+}
+
+
// isIntImmediate - This method tests to see if a constant operand.
// If so Imm will receive the 32 bit value.
static bool isIntImmediate(SDNode *N, unsigned& Imm) {
// look for the first zero bit after the run of ones
ME = CountLeadingZeros_32((Val - 1) ^ Val);
return true;
- } else if (isShiftedMask_32(Val = ~Val)) { // invert mask
- // effectively look for the first zero bit
- ME = CountLeadingZeros_32(Val) - 1;
- // effectively look for the first one bit after the run of zeros
- MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
- return true;
+ } else {
+ Val = ~Val; // invert mask
+ if (isShiftedMask_32(Val)) {
+ // effectively look for the first zero bit
+ ME = CountLeadingZeros_32(Val) - 1;
+ // effectively look for the first one bit after the run of zeros
+ MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
+ return true;
+ }
}
// no run present
return false;
return false;
}
+/// SelectBitfieldInsert - turn an or of two masked values into
+/// the rotate left word immediate then mask insert (rlwimi) instruction.
+/// Returns true on success, false if the caller still needs to select OR.
+///
+/// Patterns matched:
+/// 1. or shl, and 5. or and, and
+/// 2. or and, shl 6. or shl, shr
+/// 3. or shr, and 7. or shr, shl
+/// 4. or and, shr
+SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
+ bool IsRotate = false;
+ unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
+ unsigned Value;
+
+ SDOperand Op0 = N->getOperand(0);
+ SDOperand Op1 = N->getOperand(1);
+
+ unsigned Op0Opc = Op0.getOpcode();
+ unsigned Op1Opc = Op1.getOpcode();
+
+ // Verify that we have the correct opcodes
+ if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
+ return false;
+ if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
+ return false;
+
+ // Generate Mask value for Target
+ if (isIntImmediate(Op0.getOperand(1), Value)) {
+ switch(Op0Opc) {
+ case ISD::SHL: TgtMask <<= Value; break;
+ case ISD::SRL: TgtMask >>= Value; break;
+ case ISD::AND: TgtMask &= Value; break;
+ }
+ } else {
+ return 0;
+ }
+
+ // Generate Mask value for Insert
+ if (isIntImmediate(Op1.getOperand(1), Value)) {
+ switch(Op1Opc) {
+ case ISD::SHL:
+ SH = Value;
+ InsMask <<= SH;
+ if (Op0Opc == ISD::SRL) IsRotate = true;
+ break;
+ case ISD::SRL:
+ SH = Value;
+ InsMask >>= SH;
+ SH = 32-SH;
+ if (Op0Opc == ISD::SHL) IsRotate = true;
+ break;
+ case ISD::AND:
+ InsMask &= Value;
+ break;
+ }
+ } else {
+ return 0;
+ }
+
+ // If both of the inputs are ANDs and one of them has a logical shift by
+ // constant as its input, make that AND the inserted value so that we can
+ // combine the shift into the rotate part of the rlwimi instruction
+ bool IsAndWithShiftOp = false;
+ if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
+ if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
+ Op1.getOperand(0).getOpcode() == ISD::SRL) {
+ if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
+ SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
+ IsAndWithShiftOp = true;
+ }
+ } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
+ Op0.getOperand(0).getOpcode() == ISD::SRL) {
+ if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
+ std::swap(Op0, Op1);
+ std::swap(TgtMask, InsMask);
+ SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
+ IsAndWithShiftOp = true;
+ }
+ }
+ }
+
+ // Verify that the Target mask and Insert mask together form a full word mask
+ // and that the Insert mask is a run of set bits (which implies both are runs
+ // of set bits). Given that, Select the arguments and generate the rlwimi
+ // instruction.
+ unsigned MB, ME;
+ if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
+ bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
+ bool Op0IsAND = Op0Opc == ISD::AND;
+ // Check for rotlwi / rotrwi here, a special case of bitfield insert
+ // where both bitfield halves are sourced from the same value.
+ if (IsRotate && fullMask &&
+ N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
+ Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
+ Select(N->getOperand(0).getOperand(0)),
+ getI32Imm(SH), getI32Imm(0), getI32Imm(31));
+ return Op0.Val;
+ }
+ SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
+ : Select(Op0);
+ SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
+ : Select(Op1.getOperand(0));
+ Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
+ getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+ return Op0.Val;
+ }
+ return 0;
+}
+
// SelectIntImmediateExpr - Choose code for integer operations with an immediate
// operand.
SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
return Opr0.Val;
}
+/// SelectAddr - Given the specified address, return the two operands for a
+/// load/store instruction, and return true if it should be an indexed [r+r]
+/// operation.
+bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
+ SDOperand &Op2) {
+ unsigned imm = 0;
+ if (Addr.getOpcode() == ISD::ADD) {
+ if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
+ Op1 = getI32Imm(Lo16(imm));
+ if (FrameIndexSDNode *FI =
+ dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
+ ++FrameOff;
+ Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
+ } else {
+ Op2 = Select(Addr.getOperand(0));
+ }
+ return false;
+ } else {
+ Op1 = Select(Addr.getOperand(0));
+ Op2 = Select(Addr.getOperand(1));
+ return true; // [r+r]
+ }
+ }
+
+ // Now check if we're dealing with a global, and whether or not we should emit
+ // an optimized load or store for statics.
+ if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
+ GlobalValue *GV = GN->getGlobal();
+ if (!GV->hasWeakLinkage() && !GV->isExternal()) {
+ Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
+ if (PICEnabled)
+ Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
+ Op1);
+ else
+ Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
+ return false;
+ }
+ } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
+ Op1 = getI32Imm(0);
+ Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
+ return false;
+ } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
+ Op1 = Addr;
+ if (PICEnabled)
+ Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
+ else
+ Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
+ return false;
+ }
+ Op1 = getI32Imm(0);
+ Op2 = Select(Addr);
+ return false;
+}
+
+/// SelectCC - Select a comparison of the specified values with the specified
+/// condition code, returning the CR# of the expression.
+SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
+ ISD::CondCode CC) {
+ // Always select the LHS.
+ LHS = Select(LHS);
+
+ // Use U to determine whether the SETCC immediate range is signed or not.
+ if (MVT::isInteger(LHS.getValueType())) {
+ bool U = ISD::isUnsignedIntSetCC(CC);
+ unsigned Imm;
+ if (isIntImmediate(RHS, Imm) &&
+ ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
+ return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
+ LHS, getI32Imm(Lo16(Imm)));
+ return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
+ LHS, Select(RHS));
+ } else {
+ return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
+ }
+}
+
+/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
+/// to Condition.
+static unsigned getBCCForSetCC(ISD::CondCode CC) {
+ switch (CC) {
+ default: assert(0 && "Unknown condition!"); abort();
+ case ISD::SETEQ: return PPC::BEQ;
+ case ISD::SETNE: return PPC::BNE;
+ case ISD::SETULT:
+ case ISD::SETLT: return PPC::BLT;
+ case ISD::SETULE:
+ case ISD::SETLE: return PPC::BLE;
+ case ISD::SETUGT:
+ case ISD::SETGT: return PPC::BGT;
+ case ISD::SETUGE:
+ case ISD::SETGE: return PPC::BGE;
+ }
+ return 0;
+}
+
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
std::cerr << "\n";
abort();
case ISD::EntryToken: // These leaves remain the same.
- case ISD::UNDEF:
return Op;
case ISD::TokenFactor: {
SDOperand New;
} else {
std::vector<SDOperand> Ops;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- Ops.push_back(Select(N->getOperand(0)));
+ Ops.push_back(Select(N->getOperand(i)));
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
}
case ISD::Constant: {
assert(N->getValueType(0) == MVT::i32);
unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
- if ((unsigned)(short)v == v) {
+ unsigned Hi = HA16(v);
+ unsigned Lo = Lo16(v);
+ if (Hi && Lo) {
+ SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
+ getI32Imm(v >> 16));
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
+ } else if (Lo) {
CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
- break;
} else {
- SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
- getI32Imm(unsigned(v) >> 16));
- CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
- break;
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
}
+ break;
+ }
+ case ISD::ConstantFP: { // FIXME: this should get sucked into the legalizer
+ MachineConstantPool *CP = CurDAG->getMachineFunction().getConstantPool();
+ Constant *CFP = ConstantFP::get(Type::FloatTy,
+ cast<ConstantFPSDNode>(N)->getValue());
+ SDOperand CPN = CurDAG->getConstantPool(CP->getConstantPoolIndex(CFP),
+ MVT::i32);
+ SDOperand Tmp;
+ if (PICEnabled)
+ Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPN);
+ else
+ Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPN);
+ CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::LFS, CPN, Tmp);
+ break;
+ }
+ case ISD::UNDEF:
+ if (N->getValueType(0) == MVT::i32)
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::IMPLICIT_DEF_GPR);
+ else
+ CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::IMPLICIT_DEF_FP);
+ break;
+ case ISD::FrameIndex: {
+ int FI = cast<FrameIndexSDNode>(N)->getIndex();
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::ADDI,
+ CurDAG->getTargetFrameIndex(FI, MVT::i32),
+ getI32Imm(0));
+ break;
+ }
+ case ISD::ConstantPool: {
+ unsigned CPIIdx = cast<ConstantPoolSDNode>(N)->getIndex();
+ SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(CPIIdx, MVT::i32);
+ if (PICEnabled)
+ Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
+ else
+ Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::LA, Tmp, CPI);
+ break;
+ }
+ case ISD::GlobalAddress: {
+ GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
+ SDOperand Tmp;
+ SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
+ if (PICEnabled)
+ Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
+ else
+ Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
+
+ if (GV->hasWeakLinkage() || GV->isExternal())
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::LWZ, GA, Tmp);
+ else
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::LA, Tmp, GA);
+ break;
}
case ISD::SIGN_EXTEND_INREG:
switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
if (Ty == MVT::i32) {
unsigned Imm;
if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
- CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)),
- getI32Imm(Lo16(Imm)));
+ if (0 == Imm)
+ CurDAG->SelectNodeTo(N, Ty, PPC::NEG, Select(N->getOperand(1)));
+ else
+ CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)),
+ getI32Imm(Lo16(Imm)));
break;
}
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
case MVT::f32: Opc = PPC::FMULS; break;
case MVT::f64: Opc = PPC::FMUL; break;
}
- CurDAG->SelectNodeTo(N, N->getValueType(0), Opc, Select(N->getOperand(0)),
+ CurDAG->SelectNodeTo(N, MVT::i32, Opc, Select(N->getOperand(0)),
Select(N->getOperand(1)));
break;
}
+ case ISD::SDIV: {
+ unsigned Imm;
+ if (isIntImmediate(N->getOperand(1), Imm)) {
+ if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
+ SDOperand Op =
+ CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
+ Select(N->getOperand(0)),
+ getI32Imm(Log2_32(Imm)));
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::ADDZE,
+ Op.getValue(0), Op.getValue(1));
+ break;
+ } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
+ SDOperand Op =
+ CurDAG->getTargetNode(PPC::SRAWI, MVT::Flag, MVT::i32,
+ Select(N->getOperand(0)),
+ getI32Imm(Log2_32(-Imm)));
+ SDOperand PT =
+ CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(1),
+ Op.getValue(0));
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::NEG, PT);
+ break;
+ }
+ }
+ assert(0 && "SDIV not implemented yet!");
+ abort();
+ }
case ISD::MULHS:
assert(N->getValueType(0) == MVT::i32);
CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHW, Select(N->getOperand(0)),
Select(N->getOperand(1)));
break;
case ISD::AND: {
- unsigned Imm, SH, MB, ME;
+ unsigned Imm;
// If this is an and of a value rotated between 0 and 31 bits and then and'd
// with a mask, emit rlwinm
if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
isShiftedMask_32(~Imm))) {
SDOperand Val;
+ unsigned SH, MB, ME;
if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
Val = Select(N->getOperand(0).getOperand(0));
} else {
Select(N->getOperand(1)));
break;
}
+ case ISD::OR:
+ if (SDNode *I = SelectBitfieldInsert(N)) {
+ CurDAG->ReplaceAllUsesWith(N, I);
+ N = I;
+ break;
+ }
+ if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
+ N->getOperand(1),
+ PPC::ORIS, PPC::ORI)) {
+ CurDAG->ReplaceAllUsesWith(N, I);
+ N = I;
+ break;
+ }
+ // Finally, check for the case where we are being asked to select
+ // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
+ if (isOprNot(N->getOperand(0).Val))
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(1)),
+ Select(N->getOperand(0).getOperand(0)));
+ else if (isOprNot(N->getOperand(1).Val))
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(0)),
+ Select(N->getOperand(1).getOperand(0)));
+ else
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::OR, Select(N->getOperand(0)),
+ Select(N->getOperand(1)));
+ break;
case ISD::XOR:
// Check whether or not this node is a logical 'not'. This is represented
// by llvm as a xor with the constant value -1 (all bits set). If this is a
CurDAG->SelectNodeTo(N, MVT::i32, PPC::XOR, Select(N->getOperand(0)),
Select(N->getOperand(1)));
break;
+ case ISD::SHL: {
+ unsigned Imm, SH, MB, ME;
+ if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+ isRotateAndMask(N, Imm, true, SH, MB, ME))
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
+ Select(N->getOperand(0).getOperand(0)),
+ getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+ else if (isIntImmediate(N->getOperand(1), Imm))
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)),
+ getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
+ else
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::SLW, Select(N->getOperand(0)),
+ Select(N->getOperand(1)));
+ break;
+ }
+ case ISD::SRL: {
+ unsigned Imm, SH, MB, ME;
+ if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+ isRotateAndMask(N, Imm, true, SH, MB, ME))
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
+ Select(N->getOperand(0).getOperand(0)),
+ getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+ else if (isIntImmediate(N->getOperand(1), Imm))
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)),
+ getI32Imm(32-Imm), getI32Imm(Imm), getI32Imm(31));
+ else
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRW, Select(N->getOperand(0)),
+ Select(N->getOperand(1)));
+ break;
+ }
+ case ISD::SRA: {
+ unsigned Imm, SH, MB, ME;
+ if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
+ isRotateAndMask(N, Imm, true, SH, MB, ME))
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
+ Select(N->getOperand(0).getOperand(0)),
+ getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+ else if (isIntImmediate(N->getOperand(1), Imm))
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAWI, Select(N->getOperand(0)),
+ getI32Imm(Imm));
+ else
+ CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAW, Select(N->getOperand(0)),
+ Select(N->getOperand(1)));
+ break;
+ }
case ISD::FABS:
CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS,
Select(N->getOperand(0)));
Select(N->getOperand(0)));
break;
}
+ case ISD::LOAD:
+ case ISD::EXTLOAD:
+ case ISD::ZEXTLOAD:
+ case ISD::SEXTLOAD: {
+ SDOperand Op1, Op2;
+ bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
+
+ MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
+ N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
+ unsigned Opc;
+ switch (TypeBeingLoaded) {
+ default: N->dump(); assert(0 && "Cannot load this type!");
+ case MVT::i1:
+ case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
+ case MVT::i16:
+ if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
+ Opc = isIdx ? PPC::LHAX : PPC::LHA;
+ } else {
+ Opc = isIdx ? PPC::LHZX : PPC::LHZ;
+ }
+ break;
+ case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
+ case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
+ case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
+ }
+
+ CurDAG->SelectNodeTo(N, N->getValueType(0), MVT::Other, Opc,
+ Op1, Op2, Select(N->getOperand(0)));
+ break;
+ }
+
+ case ISD::TRUNCSTORE:
+ case ISD::STORE: {
+ SDOperand AddrOp1, AddrOp2;
+ bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
+
+ unsigned Opc;
+ if (N->getOpcode() == ISD::STORE) {
+ switch (N->getOperand(1).getValueType()) {
+ default: assert(0 && "unknown Type in store");
+ case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
+ case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
+ case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
+ }
+ } else { //ISD::TRUNCSTORE
+ switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
+ default: assert(0 && "unknown Type in store");
+ case MVT::i1:
+ case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
+ case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
+ }
+ }
+
+ CurDAG->SelectNodeTo(N, MVT::Other, Opc, Select(N->getOperand(1)),
+ AddrOp1, AddrOp2, Select(N->getOperand(0)));
+ break;
+ }
+
+ case ISD::CALLSEQ_START:
+ case ISD::CALLSEQ_END: {
+ unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
+ unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
+ PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
+ CurDAG->SelectNodeTo(N, MVT::Other, Opc,
+ getI32Imm(Amt), Select(N->getOperand(0)));
+ break;
+ }
+ case ISD::CALL:
+ case ISD::TAILCALL: {
+ SDOperand Chain = Select(N->getOperand(0));
+
+ unsigned CallOpcode;
+ std::vector<SDOperand> CallOperands;
+
+ if (GlobalAddressSDNode *GASD =
+ dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
+ CallOpcode = PPC::CALLpcrel;
+ CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
+ MVT::i32));
+ } else if (ExternalSymbolSDNode *ESSDN =
+ dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
+ CallOpcode = PPC::CALLpcrel;
+ CallOperands.push_back(N->getOperand(1));
+ } else {
+ // Copy the callee address into the CTR register.
+ SDOperand Callee = Select(N->getOperand(1));
+ Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
+
+ // Copy the callee address into R12 on darwin.
+ SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
+ Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, R12, Callee, Chain);
+
+ CallOperands.push_back(getI32Imm(20)); // Information to encode indcall
+ CallOperands.push_back(getI32Imm(0)); // Information to encode indcall
+ CallOperands.push_back(R12);
+ CallOpcode = PPC::CALLindirect;
+ }
+
+ unsigned GPR_idx = 0, FPR_idx = 0;
+ static const unsigned GPR[] = {
+ PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+ PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+ };
+ static const unsigned FPR[] = {
+ PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+ PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
+ };
+
+ for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
+ if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
+ unsigned DestReg = 0;
+ MVT::ValueType RegTy;
+ if (N->getOperand(i).getValueType() == MVT::i32) {
+ assert(GPR_idx < 8 && "Too many int args");
+ DestReg = GPR[GPR_idx++];
+ RegTy = MVT::i32;
+ } else {
+ assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
+ "Unpromoted integer arg?");
+ assert(FPR_idx < 13 && "Too many fp args");
+ DestReg = FPR[FPR_idx++];
+ RegTy = MVT::f64; // Even if this is really f32!
+ }
+
+ SDOperand Reg = CurDAG->getRegister(DestReg, RegTy);
+ Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg,
+ Select(N->getOperand(i)));
+ CallOperands.push_back(Reg);
+ }
+
+ // Finally, once everything is in registers to pass to the call, emit the
+ // call itself.
+ CallOperands.push_back(Chain);
+ Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, CallOperands);
+
+ std::vector<SDOperand> CallResults;
+
+ // If the call has results, copy the values out of the ret val registers.
+ switch (N->getValueType(0)) {
+ default: assert(0 && "Unexpected ret value!");
+ case MVT::Other: break;
+ case MVT::i32:
+ if (N->getValueType(1) == MVT::i32) {
+ Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ } else {
+ Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ }
+ break;
+ case MVT::f32:
+ case MVT::f64:
+ Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, MVT::f64).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ break;
+ }
+
+ CallResults.push_back(Chain);
+ CurDAG->ReplaceAllUsesWith(N, CallResults);
+ return CallResults[Op.ResNo];
+ }
case ISD::RET: {
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain);
break;
}
+ case ISD::BR:
+ CurDAG->SelectNodeTo(N, MVT::Other, PPC::B, N->getOperand(1),
+ Select(N->getOperand(0)));
+ break;
+ case ISD::BR_CC:
+ case ISD::BRTWOWAY_CC: {
+ SDOperand Chain = Select(N->getOperand(0));
+ MachineBasicBlock *Dest =
+ cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
+ ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
+ SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
+ unsigned Opc = getBCCForSetCC(CC);
+
+ // If this is a two way branch, then grab the fallthrough basic block
+ // argument and build a PowerPC branch pseudo-op, suitable for long branch
+ // conversion if necessary by the branch selection pass. Otherwise, emit a
+ // standard conditional branch.
+ if (N->getOpcode() == ISD::BRTWOWAY_CC) {
+ MachineBasicBlock *Fallthrough =
+ cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
+ SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
+ CondCode, getI32Imm(Opc),
+ N->getOperand(4), N->getOperand(5),
+ Chain);
+ CurDAG->SelectNodeTo(N, MVT::Other, PPC::B, N->getOperand(5), CB);
+ } else {
+ // Iterate to the next basic block
+ ilist<MachineBasicBlock>::iterator It = BB;
+ ++It;
+
+ // If the fallthrough path is off the end of the function, which would be
+ // undefined behavior, set it to be the same as the current block because
+ // we have nothing better to set it to, and leaving it alone will cause
+ // the PowerPC Branch Selection pass to crash.
+ if (It == BB->getParent()->end()) It = Dest;
+ CurDAG->SelectNodeTo(N, MVT::Other, PPC::COND_BRANCH, CondCode,
+ getI32Imm(Opc), N->getOperand(4),
+ CurDAG->getBasicBlock(It), Chain);
+ }
+ break;
+ }
}
- return SDOperand(N, 0);
+ return SDOperand(N, Op.ResNo);
}
projects / oota-llvm.git / blobdiff