namespace PPCISD {
enum NodeType {
// Start the numbering where the builtin ops and target ops leave off.
- FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
+ FIRST_NUMBER = ISD::BUILTIN_OP_END,
/// FSEL - Traditional three-operand fsel node.
///
/// indexed. This is used to implement atomic operations.
STCX,
- /// CMP_UNRESERVE = Test for equality and "unreserve" if not true. This
- /// is used to implement atomic operations.
- CMP_UNRESERVE,
-
/// TAILCALL - Indicates a tail call should be taken.
TAILCALL,
/// TC_RETURN - A tail call return.
/// formed by using a vspltis[bhw] instruction of the specified element
/// size, return the constant being splatted. The ByteSize field indicates
/// the number of bytes of each element [124] -> [bhw].
- SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
+ SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
}
class PPCTargetLowering : public TargetLowering {
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ISD::SETCC ValueType
- virtual MVT getSetCCResultType(const SDOperand &) const;
+ virtual MVT getSetCCResultType(MVT VT) const;
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
- virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
- SDOperand &Offset,
+ virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
+ SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// SelectAddressRegReg - Given the specified addressed, check to see if it
/// can be represented as an indexed [r+r] operation. Returns false if it
/// can be more efficiently represented with [r+imm].
- bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index,
- SelectionDAG &DAG);
+ bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
+ SelectionDAG &DAG) const;
/// SelectAddressRegImm - Returns true if the address N can be represented
/// by a base register plus a signed 16-bit displacement [r+imm], and if it
/// is not better represented as reg+reg.
- bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base,
- SelectionDAG &DAG);
+ bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
+ SelectionDAG &DAG) const;
/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
- bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index,
- SelectionDAG &DAG);
+ bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
+ SelectionDAG &DAG) const;
/// SelectAddressRegImmShift - Returns true if the address N can be
/// represented by a base register plus a signed 14-bit displacement
/// [r+imm*4]. Suitable for use by STD and friends.
- bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base,
- SelectionDAG &DAG);
+ bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
+ SelectionDAG &DAG) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
- virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
- virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
-
- virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ /// ReplaceNodeResults - Replace the results of node with an illegal result
+ /// type with new values built out of custom code.
+ ///
+ virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
+ SelectionDAG &DAG);
+
+ virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
- virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
unsigned Depth = 0) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
- MachineBasicBlock *MBB);
+ MachineBasicBlock *MBB) const;
+ MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
+ MachineBasicBlock *MBB, bool is64Bit,
+ unsigned BinOpcode) const;
+ MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
+ MachineBasicBlock *MBB,
+ bool is8bit, unsigned Opcode) const;
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
unsigned getByValTypeAlignment(const Type *Ty) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
- /// vector. If it is invalid, don't add anything to Ops.
- virtual void LowerAsmOperandForConstraint(SDOperand Op,
+ /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
+ /// true it means one of the asm constraint of the inline asm instruction
+ /// being processed is 'm'.
+ virtual void LowerAsmOperandForConstraint(SDValue Op,
char ConstraintLetter,
- std::vector<SDOperand> &Ops,
+ bool hasMemory,
+ std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
/// isLegalAddressingMode - Return true if the addressing mode represented
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Target which want to do tail call
/// optimization should implement this function.
- virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
- SDOperand Ret,
+ virtual bool IsEligibleForTailCallOptimization(CallSDNode *TheCall,
+ SDValue Ret,
SelectionDAG &DAG) const;
+ virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
+
private:
- /// PPCAtomicLabelIndex - Keep track the number of PPC atomic labels.
- ///
- unsigned PPCAtomicLabelIndex;
-
- SDOperand getFramePointerFrameIndex(SelectionDAG & DAG) const;
- SDOperand getReturnAddrFrameIndex(SelectionDAG & DAG) const;
-
- SDOperand EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
- int SPDiff,
- SDOperand Chain,
- SDOperand &LROpOut,
- SDOperand &FPOpOut);
-
- SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
+ SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
+ SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
+
+ SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
+ int SPDiff,
+ SDValue Chain,
+ SDValue &LROpOut,
+ SDValue &FPOpOut,
+ DebugLoc dl);
+
+ SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
int VarArgsFrameIndex, int VarArgsStackOffset,
unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
const PPCSubtarget &Subtarget);
- SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, int VarArgsFrameIndex,
+ SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex,
int VarArgsStackOffset, unsigned VarArgsNumGPR,
unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
- SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
int &VarArgsFrameIndex,
int &VarArgsStackOffset,
unsigned &VarArgsNumGPR,
unsigned &VarArgsNumFPR,
const PPCSubtarget &Subtarget);
- SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerCALL(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget, TargetMachine &TM);
- SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM);
- SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM);
+ SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget);
- SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
+ SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget);
- SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerAtomicLAS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerAtomicLCS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
- SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG);
+ SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
+ SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
};
}
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