#include "PowerPCInstrBuilder.h"
#include "PowerPCInstrInfo.h"
#include "PPC32TargetMachine.h"
+#include "PPC32ISelLowering.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include <algorithm>
using namespace llvm;
-
-//===----------------------------------------------------------------------===//
-// PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
-namespace {
- class PPC32TargetLowering : public TargetLowering {
- int VarArgsFrameIndex; // FrameIndex for start of varargs area.
- int ReturnAddrIndex; // FrameIndex for return slot.
- public:
- PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
- // Fold away setcc operations if possible.
- setSetCCIsExpensive();
-
- // Set up the register classes.
- addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
- addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
- addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
-
- // PowerPC has no intrinsics for these particular operations
- setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
- setOperationAction(ISD::MEMSET, MVT::Other, Expand);
- setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
-
- // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
- setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
- setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
-
- // PowerPC has no SREM/UREM instructions
- setOperationAction(ISD::SREM, MVT::i32, Expand);
- setOperationAction(ISD::UREM, MVT::i32, Expand);
-
- // We don't support sin/cos/sqrt/fmod
- setOperationAction(ISD::FSIN , MVT::f64, Expand);
- setOperationAction(ISD::FCOS , MVT::f64, Expand);
- setOperationAction(ISD::SREM , MVT::f64, Expand);
- setOperationAction(ISD::FSIN , MVT::f32, Expand);
- setOperationAction(ISD::FCOS , MVT::f32, Expand);
- setOperationAction(ISD::SREM , MVT::f32, Expand);
-
- // If we're enabling GP optimizations, use hardware square root
- if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
- setOperationAction(ISD::FSQRT, MVT::f64, Expand);
- setOperationAction(ISD::FSQRT, MVT::f32, Expand);
- }
-
- //PowerPC does not have CTPOP or CTTZ
- setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
- setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
-
- setSetCCResultContents(ZeroOrOneSetCCResult);
- addLegalFPImmediate(+0.0); // Necessary for FSEL
- addLegalFPImmediate(-0.0); //
-
- computeRegisterProperties();
- }
-
- /// LowerArguments - This hook must be implemented to indicate how we should
- /// lower the arguments for the specified function, into the specified DAG.
- virtual std::vector<SDOperand>
- LowerArguments(Function &F, SelectionDAG &DAG);
-
- /// LowerCallTo - This hook lowers an abstract call to a function into an
- /// actual call.
- virtual std::pair<SDOperand, SDOperand>
- LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
- bool isTailCall, SDOperand Callee, ArgListTy &Args,
- SelectionDAG &DAG);
-
- virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, SelectionDAG &DAG);
-
- virtual std::pair<SDOperand,SDOperand>
- LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG);
-
- virtual std::pair<SDOperand, SDOperand>
- LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
- SelectionDAG &DAG);
- };
-}
-
-
-std::vector<SDOperand>
-PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
- //
- // add beautiful description of PPC stack frame format, or at least some docs
- //
- MachineFunction &MF = DAG.getMachineFunction();
- MachineFrameInfo *MFI = MF.getFrameInfo();
- MachineBasicBlock& BB = MF.front();
- std::vector<SDOperand> ArgValues;
-
- // Due to the rather complicated nature of the PowerPC ABI, rather than a
- // fixed size array of physical args, for the sake of simplicity let the STL
- // handle tracking them for us.
- std::vector<unsigned> argVR, argPR, argOp;
- unsigned ArgOffset = 24;
- unsigned GPR_remaining = 8;
- unsigned FPR_remaining = 13;
- unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
- PPC::R3, PPC::R4, PPC::R5, PPC::R6,
- PPC::R7, PPC::R8, PPC::R9, PPC::R10,
- };
- static const unsigned FPR[] = {
- PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
- };
-
- // Add DAG nodes to load the arguments... On entry to a function on PPC,
- // the arguments start at offset 24, although they are likely to be passed
- // in registers.
- for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
- SDOperand newroot, argt;
- unsigned ObjSize;
- bool needsLoad = false;
- bool ArgLive = !I->use_empty();
- MVT::ValueType ObjectVT = getValueType(I->getType());
-
- switch (ObjectVT) {
- default: assert(0 && "Unhandled argument type!");
- case MVT::i1:
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
- ObjSize = 4;
- if (!ArgLive) break;
- if (GPR_remaining > 0) {
- MF.addLiveIn(GPR[GPR_idx]);
- argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
- DAG.getRoot());
- if (ObjectVT != MVT::i32)
- argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
- } else {
- needsLoad = true;
- }
- break;
- case MVT::i64: ObjSize = 8;
- if (!ArgLive) break;
- if (GPR_remaining > 0) {
- SDOperand argHi, argLo;
- MF.addLiveIn(GPR[GPR_idx]);
- argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
- // If we have two or more remaining argument registers, then both halves
- // of the i64 can be sourced from there. Otherwise, the lower half will
- // have to come off the stack. This can happen when an i64 is preceded
- // by 28 bytes of arguments.
- if (GPR_remaining > 1) {
- MF.addLiveIn(GPR[GPR_idx+1]);
- argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
- } else {
- int FI = MFI->CreateFixedObject(4, ArgOffset+4);
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
- argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
- DAG.getSrcValue(NULL));
- }
- // Build the outgoing arg thingy
- argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
- newroot = argLo;
- } else {
- needsLoad = true;
- }
- break;
- case MVT::f32:
- case MVT::f64:
- ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
- if (!ArgLive) break;
- if (FPR_remaining > 0) {
- MF.addLiveIn(FPR[FPR_idx]);
- argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
- DAG.getRoot());
- --FPR_remaining;
- ++FPR_idx;
- } else {
- needsLoad = true;
- }
- break;
- }
-
- // We need to load the argument to a virtual register if we determined above
- // that we ran out of physical registers of the appropriate type
- if (needsLoad) {
- unsigned SubregOffset = 0;
- if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
- if (ObjectVT == MVT::i16) SubregOffset = 2;
- int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
- FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
- DAG.getConstant(SubregOffset, MVT::i32));
- argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
- DAG.getSrcValue(NULL));
- }
-
- // Every 4 bytes of argument space consumes one of the GPRs available for
- // argument passing.
- if (GPR_remaining > 0) {
- unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
- GPR_remaining -= delta;
- GPR_idx += delta;
- }
- ArgOffset += ObjSize;
- if (newroot.Val)
- DAG.setRoot(newroot.getValue(1));
-
- ArgValues.push_back(argt);
- }
-
- // If the function takes variable number of arguments, make a frame index for
- // the start of the first vararg value... for expansion of llvm.va_start.
- if (F.isVarArg()) {
- VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
- SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
- // If this function is vararg, store any remaining integer argument regs
- // to their spots on the stack so that they may be loaded by deferencing the
- // result of va_next.
- std::vector<SDOperand> MemOps;
- for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
- MF.addLiveIn(GPR[GPR_idx]);
- SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
- Val, FIN, DAG.getSrcValue(NULL));
- MemOps.push_back(Store);
- // Increment the address by four for the next argument to store
- SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
- FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
- }
- DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
- }
-
- // Finally, inform the code generator which regs we return values in.
- switch (getValueType(F.getReturnType())) {
- default: assert(0 && "Unknown type!");
- case MVT::isVoid: break;
- case MVT::i1:
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
- MF.addLiveOut(PPC::R3);
- break;
- case MVT::i64:
- MF.addLiveOut(PPC::R3);
- MF.addLiveOut(PPC::R4);
- break;
- case MVT::f32:
- case MVT::f64:
- MF.addLiveOut(PPC::F1);
- break;
- }
-
- return ArgValues;
-}
-
-std::pair<SDOperand, SDOperand>
-PPC32TargetLowering::LowerCallTo(SDOperand Chain,
- const Type *RetTy, bool isVarArg,
- unsigned CallingConv, bool isTailCall,
- SDOperand Callee, ArgListTy &Args,
- SelectionDAG &DAG) {
- // args_to_use will accumulate outgoing args for the ISD::CALL case in
- // SelectExpr to use to put the arguments in the appropriate registers.
- std::vector<SDOperand> args_to_use;
-
- // Count how many bytes are to be pushed on the stack, including the linkage
- // area, and parameter passing area.
- unsigned NumBytes = 24;
-
- if (Args.empty()) {
- Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
- DAG.getConstant(NumBytes, getPointerTy()));
- } else {
- for (unsigned i = 0, e = Args.size(); i != e; ++i)
- switch (getValueType(Args[i].second)) {
- default: assert(0 && "Unknown value type!");
- case MVT::i1:
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
- case MVT::f32:
- NumBytes += 4;
- break;
- case MVT::i64:
- case MVT::f64:
- NumBytes += 8;
- break;
- }
-
- // Just to be safe, we'll always reserve the full 24 bytes of linkage area
- // plus 32 bytes of argument space in case any called code gets funky on us.
- // (Required by ABI to support var arg)
- if (NumBytes < 56) NumBytes = 56;
-
- // Adjust the stack pointer for the new arguments...
- // These operations are automatically eliminated by the prolog/epilog pass
- Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
- DAG.getConstant(NumBytes, getPointerTy()));
-
- // Set up a copy of the stack pointer for use loading and storing any
- // arguments that may not fit in the registers available for argument
- // passing.
- SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
- DAG.getEntryNode());
-
- // Figure out which arguments are going to go in registers, and which in
- // memory. Also, if this is a vararg function, floating point operations
- // must be stored to our stack, and loaded into integer regs as well, if
- // any integer regs are available for argument passing.
- unsigned ArgOffset = 24;
- unsigned GPR_remaining = 8;
- unsigned FPR_remaining = 13;
-
- std::vector<SDOperand> MemOps;
- for (unsigned i = 0, e = Args.size(); i != e; ++i) {
- // PtrOff will be used to store the current argument to the stack if a
- // register cannot be found for it.
- SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
- MVT::ValueType ArgVT = getValueType(Args[i].second);
-
- switch (ArgVT) {
- default: assert(0 && "Unexpected ValueType for argument!");
- case MVT::i1:
- case MVT::i8:
- case MVT::i16:
- // Promote the integer to 32 bits. If the input type is signed use a
- // sign extend, otherwise use a zero extend.
- if (Args[i].second->isSigned())
- Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
- else
- Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
- // FALL THROUGH
- case MVT::i32:
- if (GPR_remaining > 0) {
- args_to_use.push_back(Args[i].first);
- --GPR_remaining;
- } else {
- MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Args[i].first, PtrOff,
- DAG.getSrcValue(NULL)));
- }
- ArgOffset += 4;
- break;
- case MVT::i64:
- // If we have one free GPR left, we can place the upper half of the i64
- // in it, and store the other half to the stack. If we have two or more
- // free GPRs, then we can pass both halves of the i64 in registers.
- if (GPR_remaining > 0) {
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
- Args[i].first, DAG.getConstant(1, MVT::i32));
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
- Args[i].first, DAG.getConstant(0, MVT::i32));
- args_to_use.push_back(Hi);
- --GPR_remaining;
- if (GPR_remaining > 0) {
- args_to_use.push_back(Lo);
- --GPR_remaining;
- } else {
- SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
- MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Lo, PtrOff, DAG.getSrcValue(NULL)));
- }
- } else {
- MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Args[i].first, PtrOff,
- DAG.getSrcValue(NULL)));
- }
- ArgOffset += 8;
- break;
- case MVT::f32:
- case MVT::f64:
- if (FPR_remaining > 0) {
- args_to_use.push_back(Args[i].first);
- --FPR_remaining;
- if (isVarArg) {
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Args[i].first, PtrOff,
- DAG.getSrcValue(NULL));
- MemOps.push_back(Store);
- // Float varargs are always shadowed in available integer registers
- if (GPR_remaining > 0) {
- SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
- DAG.getSrcValue(NULL));
- MemOps.push_back(Load);
- args_to_use.push_back(Load);
- --GPR_remaining;
- }
- if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
- SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
- SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
- DAG.getSrcValue(NULL));
- MemOps.push_back(Load);
- args_to_use.push_back(Load);
- --GPR_remaining;
- }
- } else {
- // If we have any FPRs remaining, we may also have GPRs remaining.
- // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
- // GPRs.
- if (GPR_remaining > 0) {
- args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
- --GPR_remaining;
- }
- if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
- args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
- --GPR_remaining;
- }
- }
- } else {
- MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Args[i].first, PtrOff,
- DAG.getSrcValue(NULL)));
- }
- ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
- break;
- }
- }
- if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
- }
-
- std::vector<MVT::ValueType> RetVals;
- MVT::ValueType RetTyVT = getValueType(RetTy);
- if (RetTyVT != MVT::isVoid)
- RetVals.push_back(RetTyVT);
- RetVals.push_back(MVT::Other);
-
- SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
- Chain, Callee, args_to_use), 0);
- Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
- Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
- DAG.getConstant(NumBytes, getPointerTy()));
- return std::make_pair(TheCall, Chain);
-}
-
-SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
- Value *VAListV, SelectionDAG &DAG) {
- // vastart just stores the address of the VarArgsFrameIndex slot into the
- // memory location argument.
- SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
- return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
- DAG.getSrcValue(VAListV));
-}
-
-std::pair<SDOperand,SDOperand>
-PPC32TargetLowering::LowerVAArg(SDOperand Chain,
- SDOperand VAListP, Value *VAListV,
- const Type *ArgTy, SelectionDAG &DAG) {
- MVT::ValueType ArgVT = getValueType(ArgTy);
-
- SDOperand VAList =
- DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
- SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
- unsigned Amt;
- if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
- Amt = 4;
- else {
- assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
- "Other types should have been promoted for varargs!");
- Amt = 8;
- }
- VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
- DAG.getConstant(Amt, VAList.getValueType()));
- Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- VAList, VAListP, DAG.getSrcValue(VAListV));
- return std::make_pair(Result, Chain);
-}
-
-
-std::pair<SDOperand, SDOperand> PPC32TargetLowering::
-LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
- SelectionDAG &DAG) {
- assert(0 && "LowerFrameReturnAddress unimplemented");
- abort();
-}
-
namespace {
Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted");
Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
ISelDAG = 0;
}
+ // convenience functions for virtual register creation
+ inline unsigned MakeIntReg() {
+ return RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
+ }
+ inline unsigned MakeFPReg() {
+ return RegMap->createVirtualRegister(PPC32::FPRCRegisterClass);
+ }
+
// dag -> dag expanders for integer divide by constant
SDOperand BuildSDIVSequence(SDOperand N);
SDOperand BuildUDIVSequence(SDOperand N);
unsigned getGlobalBaseReg();
unsigned getConstDouble(double floatVal, unsigned Result);
- void MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result);
+ void MoveCRtoGPR(unsigned CCReg, ISD::CondCode CC, unsigned Result);
bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
unsigned FoldIfWideZeroExtend(SDOperand N);
- unsigned SelectCC(SDOperand CC, unsigned &Opc, bool &Inv, unsigned &Idx);
- unsigned SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv, unsigned &Idx);
- bool SelectIntImmediateExpr(SDOperand N, unsigned Result, unsigned C,
+ unsigned SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
+ bool SelectIntImmediateExpr(SDOperand N, unsigned Result,
unsigned OCHi, unsigned OCLo,
- bool IsArithmetic);
+ bool IsArithmetic = false, bool Negate = false);
unsigned SelectExpr(SDOperand N, bool Recording=false);
void Select(SDOperand N);
}
// if the mask doesn't intersect any Indeterminant bits
- if (!(Mask & Indeterminant)) {
+ if (Mask && !(Mask & Indeterminant)) {
SH = Shift;
// make sure the mask is still a mask (wrap arounds may not be)
return isRunOfOnes(Mask, MB, ME);
return false;
}
+// isOpcWithIntImmediate - This method tests to see if the node is a specific
+// opcode and that it has a immediate integer right operand.
+// If so Imm will receive the 32 bit value.
+static bool isOpcWithIntImmediate(SDOperand N, unsigned Opc, unsigned& Imm) {
+ return N.getOpcode() == Opc && isIntImmediate(N.getOperand(1), Imm);
+}
+
// isOprShiftImm - Returns true if the specified operand is a shift opcode with
// a immediate shift count less than 32.
static bool isOprShiftImm(SDOperand N, unsigned& Opc, unsigned& SH) {
// isOprNot - Returns true if the specified operand is an xor with immediate -1.
static bool isOprNot(SDOperand N) {
unsigned Imm;
- return N.getOpcode() == ISD::XOR &&
- isIntImmediate(N.getOperand(1), Imm) && (signed)Imm == -1;
+ return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
}
// Immediate constant composers.
}
/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
-/// to Condition. If the Condition is unordered or unsigned, the bool argument
-/// U is set to true, otherwise it is set to false.
-static unsigned getBCCForSetCC(unsigned Condition, bool& U) {
- U = false;
- switch (Condition) {
+/// to Condition.
+static unsigned getBCCForSetCC(ISD::CondCode CC) {
+ switch (CC) {
default: assert(0 && "Unknown condition!"); abort();
case ISD::SETEQ: return PPC::BEQ;
case ISD::SETNE: return PPC::BNE;
- case ISD::SETULT: U = true;
+ case ISD::SETULT:
case ISD::SETLT: return PPC::BLT;
- case ISD::SETULE: U = true;
+ case ISD::SETULE:
case ISD::SETLE: return PPC::BLE;
- case ISD::SETUGT: U = true;
+ case ISD::SETUGT:
case ISD::SETGT: return PPC::BGT;
- case ISD::SETUGE: U = true;
+ case ISD::SETUGE:
case ISD::SETGE: return PPC::BGE;
}
return 0;
/// getCRIdxForSetCC - Return the index of the condition register field
/// associated with the SetCC condition, and whether or not the field is
/// treated as inverted. That is, lt = 0; ge = 0 inverted.
-static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
- switch (Condition) {
+static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
+ switch (CC) {
default: assert(0 && "Unknown condition!"); abort();
case ISD::SETULT:
case ISD::SETLT: Inv = false; return 0;
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
- GlobalBaseReg = MakeReg(MVT::i32);
+ GlobalBaseReg = MakeIntReg();
BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
GlobalBaseInitialized = true;
/// getConstDouble - Loads a floating point value into a register, via the
/// Constant Pool. Optionally takes a register in which to load the value.
unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
- unsigned Tmp1 = MakeReg(MVT::i32);
- if (0 == Result) Result = MakeReg(MVT::f64);
+ unsigned Tmp1 = MakeIntReg();
+ if (0 == Result) Result = MakeFPReg();
MachineConstantPool *CP = BB->getParent()->getConstantPool();
ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
unsigned CPI = CP->getConstantPoolIndex(CFP);
/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
/// Inv is true, then invert the result.
-void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
- unsigned IntCR = MakeReg(MVT::i32);
+void ISel::MoveCRtoGPR(unsigned CCReg, ISD::CondCode CC, unsigned Result){
+ bool Inv;
+ unsigned IntCR = MakeIntReg();
+ unsigned Idx = getCRIdxForSetCC(CC, Inv);
BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
bool GPOpt =
TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor();
BuildMI(BB, GPOpt ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
if (Inv) {
- unsigned Tmp1 = MakeReg(MVT::i32);
+ unsigned Tmp1 = MakeIntReg();
BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
.addImm(31).addImm(31);
BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(1);
bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
bool IsRotate = false;
unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
+ unsigned Value;
SDOperand Op0 = OR.getOperand(0);
SDOperand Op1 = OR.getOperand(1);
return false;
// Generate Mask value for Target
- if (ConstantSDNode *CN =
- dyn_cast<ConstantSDNode>(Op0.getOperand(1).Val)) {
+ if (isIntImmediate(Op0.getOperand(1), Value)) {
switch(Op0Opc) {
- case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
- case ISD::SRL: TgtMask >>= (unsigned)CN->getValue(); break;
- case ISD::AND: TgtMask &= (unsigned)CN->getValue(); break;
+ case ISD::SHL: TgtMask <<= Value; break;
+ case ISD::SRL: TgtMask >>= Value; break;
+ case ISD::AND: TgtMask &= Value; break;
}
} else {
return false;
}
// Generate Mask value for Insert
- if (ConstantSDNode *CN =
- dyn_cast<ConstantSDNode>(Op1.getOperand(1).Val)) {
+ if (isIntImmediate(Op1.getOperand(1), Value)) {
switch(Op1Opc) {
case ISD::SHL:
- Amount = CN->getValue();
+ Amount = Value;
InsMask <<= Amount;
if (Op0Opc == ISD::SRL) IsRotate = true;
break;
case ISD::SRL:
- Amount = CN->getValue();
+ Amount = Value;
InsMask >>= Amount;
Amount = 32-Amount;
if (Op0Opc == ISD::SHL) IsRotate = true;
break;
case ISD::AND:
- InsMask &= (unsigned)CN->getValue();
+ InsMask &= Value;
break;
}
} else {
if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
Op1.getOperand(0).getOpcode() == ISD::SRL) {
- if (ConstantSDNode *CN =
- dyn_cast<ConstantSDNode>(Op1.getOperand(0).getOperand(1).Val)) {
+ if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ?
- CN->getValue() : 32 - CN->getValue();
+ Value : 32 - Value;
Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0));
}
} else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
Op0.getOperand(0).getOpcode() == ISD::SRL) {
- if (ConstantSDNode *CN =
- dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(1).Val)) {
+ if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
std::swap(Op0, Op1);
std::swap(TgtMask, InsMask);
Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ?
- CN->getValue() : 32 - CN->getValue();
+ Value : 32 - Value;
Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0));
}
}
/// wider than the implicit mask, then we can get rid of the AND and let the
/// shift do the mask.
unsigned ISel::FoldIfWideZeroExtend(SDOperand N) {
- unsigned C, MB, ME;
- if (N.getOpcode() == ISD::AND &&
- isIntImmediate(N.getOperand(1), C) && isRunOfOnes(C, MB, ME) &&
- MB <= 26 && ME == 31)
+ unsigned C;
+ if (isOpcWithIntImmediate(N, ISD::AND, C) && isMask_32(C) && C > 63)
return SelectExpr(N.getOperand(0));
else
return SelectExpr(N);
}
-unsigned ISel::SelectCC(SDOperand Cond, unsigned& Opc, bool &Inv, unsigned& Idx) {
+unsigned ISel::SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC) {
unsigned Result, Tmp1, Tmp2;
bool AlreadySelected = false;
static const unsigned CompareOpcodes[] =
// Allocate a condition register for this expression
Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
- // If the first operand to the select is a SETCC node, then we can fold it
- // into the branch that selects which value to return.
- if (Cond.getOpcode() == ISD::SETCC) {
- ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
- bool U;
- Opc = getBCCForSetCC(CC, U);
- Idx = getCRIdxForSetCC(CC, Inv);
-
- // Use U to determine whether the SETCC immediate range is signed or not.
- if (isIntImmediate(Cond.getOperand(1), Tmp2) &&
- ((U && isUInt16(Tmp2)) || (!U && isInt16(Tmp2)))) {
- Tmp2 = Lo16(Tmp2);
- // For comparisons against zero, we can implicity set CR0 if a recording
- // variant (e.g. 'or.' instead of 'or') of the instruction that defines
- // operand zero of the SetCC node is available.
- if (Tmp2 == 0 &&
- NodeHasRecordingVariant(Cond.getOperand(0).getOpcode()) &&
- Cond.getOperand(0).Val->hasOneUse()) {
- RecordSuccess = false;
- Tmp1 = SelectExpr(Cond.getOperand(0), true);
- if (RecordSuccess) {
- ++Recorded;
- BuildMI(BB, PPC::MCRF, 1, Result).addReg(PPC::CR0);
- return Result;
- }
- AlreadySelected = true;
+ // Use U to determine whether the SETCC immediate range is signed or not.
+ bool U = ISD::isUnsignedIntSetCC(CC);
+ if (isIntImmediate(RHS, Tmp2) &&
+ ((U && isUInt16(Tmp2)) || (!U && isInt16(Tmp2)))) {
+ Tmp2 = Lo16(Tmp2);
+ // For comparisons against zero, we can implicity set CR0 if a recording
+ // variant (e.g. 'or.' instead of 'or') of the instruction that defines
+ // operand zero of the SetCC node is available.
+ if (Tmp2 == 0 &&
+ NodeHasRecordingVariant(LHS.getOpcode()) && LHS.Val->hasOneUse()) {
+ RecordSuccess = false;
+ Tmp1 = SelectExpr(LHS, true);
+ if (RecordSuccess) {
+ ++Recorded;
+ BuildMI(BB, PPC::MCRF, 1, Result).addReg(PPC::CR0);
+ return Result;
}
- // If we could not implicitly set CR0, then emit a compare immediate
- // instead.
- if (!AlreadySelected) Tmp1 = SelectExpr(Cond.getOperand(0));
- if (U)
- BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
- else
- BuildMI(BB, PPC::CMPWI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
- } else {
- bool IsInteger = MVT::isInteger(Cond.getOperand(0).getValueType());
- unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
- Tmp1 = SelectExpr(Cond.getOperand(0));
- Tmp2 = SelectExpr(Cond.getOperand(1));
- BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ AlreadySelected = true;
}
+ // If we could not implicitly set CR0, then emit a compare immediate
+ // instead.
+ if (!AlreadySelected) Tmp1 = SelectExpr(LHS);
+ if (U)
+ BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
+ else
+ BuildMI(BB, PPC::CMPWI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
} else {
- // If this isn't a SetCC, then select the value and compare it against zero,
- // treating it as if it were a boolean.
- Opc = PPC::BNE;
- Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
- Tmp1 = SelectExpr(Cond);
- BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
- }
- return Result;
-}
-
-unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
- unsigned &Idx) {
- bool Inv0, Inv1;
- unsigned Idx0, Idx1, CROpc, Opc1, Tmp1, Tmp2;
-
- // Allocate a condition register for this expression
- unsigned Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
-
- // Check for the operations we support:
- switch(N.getOpcode()) {
- default:
- Opc = PPC::BNE;
- Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
- Tmp1 = SelectExpr(N);
- BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
- break;
- case ISD::OR:
- case ISD::AND:
- Tmp1 = SelectCCExpr(N.getOperand(0), Opc, Inv0, Idx0);
- Tmp2 = SelectCCExpr(N.getOperand(1), Opc1, Inv1, Idx1);
- CROpc = getCROpForSetCC(N.getOpcode(), Inv0, Inv1);
- if (Inv0 && !Inv1) {
- std::swap(Tmp1, Tmp2);
- std::swap(Idx0, Idx1);
- Opc = Opc1;
- }
- if (Inv0 && Inv1) Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
- BuildMI(BB, CROpc, 5, Result).addImm(Idx0).addReg(Tmp1).addImm(Idx0)
- .addReg(Tmp2).addImm(Idx1);
- Inv = false;
- Idx = Idx0;
- break;
- case ISD::SETCC:
- Tmp1 = SelectCC(N, Opc, Inv, Idx);
- Result = Tmp1;
- break;
+ bool IsInteger = MVT::isInteger(LHS.getValueType());
+ unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
+ Tmp1 = SelectExpr(LHS);
+ Tmp2 = SelectExpr(RHS);
+ BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
}
if(GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(N)) {
GlobalValue *GV = GN->getGlobal();
if (!GV->hasWeakLinkage() && !GV->isExternal()) {
- unsigned GlobalHi = MakeReg(MVT::i32);
+ unsigned GlobalHi = MakeIntReg();
if (PICEnabled)
BuildMI(BB, PPC::ADDIS, 2, GlobalHi).addReg(getGlobalBaseReg())
.addGlobalAddress(GV);
void ISel::SelectBranchCC(SDOperand N)
{
MachineBasicBlock *Dest =
- cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
+ cast<BasicBlockSDNode>(N.getOperand(4))->getBasicBlock();
- bool Inv;
- unsigned Opc, CCReg, Idx;
Select(N.getOperand(0)); //chain
- CCReg = SelectCC(N.getOperand(1), Opc, Inv, Idx);
+ ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(1))->get();
+ unsigned CCReg = SelectCC(N.getOperand(2), N.getOperand(3), CC);
+ unsigned Opc = getBCCForSetCC(CC);
// Iterate to the next basic block
ilist<MachineBasicBlock>::iterator It = BB;
// and build a PowerPC branch pseudo-op, suitable for long branch conversion
// if necessary by the branch selection pass. Otherwise, emit a standard
// conditional branch.
- if (N.getOpcode() == ISD::BRCONDTWOWAY) {
+ if (N.getOpcode() == ISD::BRTWOWAY_CC) {
MachineBasicBlock *Fallthrough =
- cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
+ cast<BasicBlockSDNode>(N.getOperand(5))->getBasicBlock();
if (Dest != It) {
BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
.addMBB(Dest).addMBB(Fallthrough);
}
// SelectIntImmediateExpr - Choose code for opcodes with immediate value.
-// Note: immediate constant must be second operand so that the use count can be
-// determined.
-bool ISel::SelectIntImmediateExpr(SDOperand N, unsigned Result, unsigned C,
+bool ISel::SelectIntImmediateExpr(SDOperand N, unsigned Result,
unsigned OCHi, unsigned OCLo,
- bool IsArithmetic) {
+ bool IsArithmetic, bool Negate) {
+ // check constant
+ ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1));
+ // exit if not a constant
+ if (!CN) return false;
+ // extract immediate
+ unsigned C = (unsigned)CN->getSignExtended();
+ // negate if required (ISD::SUB)
+ if (Negate) C = -C;
// get the hi and lo portions of constant
unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
unsigned Lo = Lo16(C);
if (Hi && Lo) {
// exit if usage indicates it would be better to load immediate into a
// register
- if (dyn_cast<ConstantSDNode>(N.getOperand(1))->use_size() > 2)
- return false;
+ if (CN->use_size() > 2) return false;
// need intermediate result for two instructions
- Tmp = MakeReg(MVT::i32);
+ Tmp = MakeIntReg();
}
// get first operand
unsigned Opr0 = SelectExpr(N.getOperand(0));
SDNode *Node = N.Val;
MVT::ValueType DestType = N.getValueType();
- if (Node->getOpcode() == ISD::CopyFromReg &&
- (MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()) ||
- cast<RegSDNode>(Node)->getReg() == PPC::R1))
+ if (Node->getOpcode() == ISD::CopyFromReg) {
+ unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
// Just use the specified register as our input.
- return cast<RegSDNode>(Node)->getReg();
+ if (MRegisterInfo::isVirtualRegister(Reg) || Reg == PPC::R1)
+ return Reg;
+ }
unsigned &Reg = ExprMap[N];
if (Reg) return Reg;
switch (opcode) {
default:
- Node->dump();
+ Node->dump(); std::cerr << '\n';
assert(0 && "Node not handled!\n");
case ISD::UNDEF:
BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
case ISD::ConstantPool:
Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
- Tmp2 = MakeReg(MVT::i32);
+ Tmp2 = MakeIntReg();
if (PICEnabled)
BuildMI(BB, PPC::ADDIS, 2, Tmp2).addReg(getGlobalBaseReg())
.addConstantPoolIndex(Tmp1);
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
- Tmp1 = MakeReg(MVT::i32);
+ Tmp1 = MakeIntReg();
if (PICEnabled)
BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
.addGlobalAddress(GV);
}
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
- Tmp1 = MakeReg(MVT::i32);
+ Tmp1 = MakeIntReg();
int CPI = CP->getIndex();
if (PICEnabled)
BuildMI(BB, PPC::ADDIS, 2, Tmp1).addReg(getGlobalBaseReg())
DestType = N.getValue(0).getValueType();
if (Result == 1)
Result = ExprMap[N.getValue(0)] = MakeReg(DestType);
- Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
+ Tmp1 = dyn_cast<RegisterSDNode>(Node->getOperand(1))->getReg();
if (MVT::isInteger(DestType))
BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
else
return Result;
case ISD::SHL:
- Tmp1 = SelectExpr(N.getOperand(0));
- if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
- Tmp2 = CN->getValue() & 0x1F;
+ if (isIntImmediate(N.getOperand(1), Tmp2)) {
+ unsigned SH, MB, ME;
+ if (isOpcWithIntImmediate(N.getOperand(0), ISD::AND, Tmp3) &&
+ isRotateAndMask(ISD::SHL, Tmp2, Tmp3, true, SH, MB, ME)) {
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(SH)
+ .addImm(MB).addImm(ME);
+ return Result;
+ }
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 &= 0x1F;
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
.addImm(31-Tmp2);
} else {
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
case ISD::SRL:
- Tmp1 = SelectExpr(N.getOperand(0));
- if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
- Tmp2 = CN->getValue() & 0x1F;
+ if (isIntImmediate(N.getOperand(1), Tmp2)) {
+ unsigned SH, MB, ME;
+ if (isOpcWithIntImmediate(N.getOperand(0), ISD::AND, Tmp3) &&
+ isRotateAndMask(ISD::SRL, Tmp2, Tmp3, true, SH, MB, ME)) {
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(SH)
+ .addImm(MB).addImm(ME);
+ return Result;
+ }
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 &= 0x1F;
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(32-Tmp2)
.addImm(Tmp2).addImm(31);
} else {
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
case ISD::SRA:
- Tmp1 = SelectExpr(N.getOperand(0));
- if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
- Tmp2 = CN->getValue() & 0x1F;
+ if (isIntImmediate(N.getOperand(1), Tmp2)) {
+ unsigned SH, MB, ME;
+ if (isOpcWithIntImmediate(N.getOperand(0), ISD::AND, Tmp3) &&
+ isRotateAndMask(ISD::SRA, Tmp2, Tmp3, true, SH, MB, ME)) {
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(SH)
+ .addImm(MB).addImm(ME);
+ return Result;
+ }
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 &= 0x1F;
BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
} else {
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
}
- if (isIntImmediate(N.getOperand(1), Tmp2)) {
- if (SelectIntImmediateExpr(N, Result, Tmp2, PPC::ADDIS, PPC::ADDI, true))
- return Result;
- }
-
+ if (SelectIntImmediateExpr(N, Result, PPC::ADDIS, PPC::ADDI, true))
+ return Result;
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
}
}
+ if (isOprNot(N.getOperand(1))) {
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
+ BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ RecordSuccess = false;
+ return Result;
+ }
if (isOprNot(N.getOperand(0))) {
- Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp2).addReg(Tmp1);
+ Tmp1 = SelectExpr(N.getOperand(1));
+ Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2);
RecordSuccess = false;
return Result;
}
case ISD::OR:
if (SelectBitfieldInsert(N, Result))
return Result;
- if (isIntImmediate(N.getOperand(1), Tmp2)) {
- if (SelectIntImmediateExpr(N, Result, Tmp2, PPC::ORIS, PPC::ORI, false))
- return Result;
+ if (SelectIntImmediateExpr(N, Result, PPC::ORIS, PPC::ORI))
+ return Result;
+ if (isOprNot(N.getOperand(1))) {
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
+ BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ RecordSuccess = false;
+ return Result;
+ }
+ if (isOprNot(N.getOperand(0))) {
+ Tmp1 = SelectExpr(N.getOperand(1));
+ Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ RecordSuccess = false;
+ return Result;
}
// emit regular or
Tmp1 = SelectExpr(N.getOperand(0));
case ISD::XOR: {
// Check for EQV: xor, (xor a, -1), b
- if (N.getOperand(0).getOpcode() == ISD::XOR &&
- isIntImmediate(N.getOperand(0).getOperand(1), Tmp2) &&
- (signed)Tmp2 == -1) {
+ if (isOprNot(N.getOperand(0))) {
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
}
- if (isIntImmediate(N.getOperand(1), Tmp2)) {
- if (SelectIntImmediateExpr(N, Result, Tmp2, PPC::XORIS, PPC::XORI, false))
- return Result;
- }
+ if (SelectIntImmediateExpr(N, Result, PPC::XORIS, PPC::XORI))
+ return Result;
// emit regular xor
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
return Result;
}
if (isIntImmediate(N.getOperand(0), Tmp1) && isInt16(Tmp1)) {
+ Tmp1 = Lo16(Tmp1);
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
return Result;
- } else if (isIntImmediate(N.getOperand(1), Tmp2)) {
- if (SelectIntImmediateExpr(N, Result, -Tmp2, PPC::ADDIS, PPC::ADDI, true))
+ }
+ if (SelectIntImmediateExpr(N, Result, PPC::ADDIS, PPC::ADDI, true, true))
return Result;
- }
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
if (isIntImmediate(N.getOperand(1), Tmp3)) {
if ((signed)Tmp3 > 0 && isPowerOf2_32(Tmp3)) {
Tmp3 = Log2_32(Tmp3);
- Tmp1 = MakeReg(MVT::i32);
+ Tmp1 = MakeIntReg();
Tmp2 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::SRAWI, 2, Tmp1).addReg(Tmp2).addImm(Tmp3);
BuildMI(BB, PPC::ADDZE, 1, Result).addReg(Tmp1);
} else if ((signed)Tmp3 < 0 && isPowerOf2_32(-Tmp3)) {
Tmp3 = Log2_32(-Tmp3);
Tmp2 = SelectExpr(N.getOperand(0));
- Tmp1 = MakeReg(MVT::i32);
- unsigned Tmp4 = MakeReg(MVT::i32);
+ Tmp1 = MakeIntReg();
+ unsigned Tmp4 = MakeIntReg();
BuildMI(BB, PPC::SRAWI, 2, Tmp1).addReg(Tmp2).addImm(Tmp3);
BuildMI(BB, PPC::ADDZE, 1, Tmp4).addReg(Tmp1);
BuildMI(BB, PPC::NEG, 1, Result).addReg(Tmp4);
case ISD::SUB_PARTS: {
assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
"Not an i64 add/sub!");
- // Emit all of the operands.
- std::vector<unsigned> InVals;
- for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
- InVals.push_back(SelectExpr(N.getOperand(i)));
+ unsigned Tmp4 = 0;
+ bool ME = isIntImmediate(N.getOperand(3),Tmp3) && ((signed)Tmp3 == -1);
+ bool ZE = isIntImmediate(N.getOperand(3),Tmp3) && (Tmp3 == 0);
+ bool IM = isIntImmediate(N.getOperand(2),Tmp3) && ((signed)Tmp3 >= -32768 ||
+ (signed)Tmp3 < 32768);
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1));
+ if (!IM || N.getOpcode() == ISD::SUB_PARTS)
+ Tmp3 = SelectExpr(N.getOperand(2));
+ if ((!ME && !ZE) || N.getOpcode() == ISD::SUB_PARTS)
+ Tmp4 = SelectExpr(N.getOperand(3));
+
if (N.getOpcode() == ISD::ADD_PARTS) {
- BuildMI(BB, PPC::ADDC, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
- BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
+ // Codegen the low 32 bits of the add. Interestingly, there is no shifted
+ // form of add immediate carrying.
+ if (IM)
+ BuildMI(BB, PPC::ADDIC, 2, Result).addReg(Tmp1).addSImm(Tmp3);
+ else
+ BuildMI(BB, PPC::ADDC, 2, Result).addReg(Tmp1).addReg(Tmp3);
+ // Codegen the high 32 bits, adding zero, minus one, or the full value
+ // along with the carry flag produced by addc/addic to tmp2.
+ if (ZE)
+ BuildMI(BB, PPC::ADDZE, 1, Result+1).addReg(Tmp2);
+ else if (ME)
+ BuildMI(BB, PPC::ADDME, 1, Result+1).addReg(Tmp2);
+ else
+ BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(Tmp2).addReg(Tmp4);
} else {
- BuildMI(BB, PPC::SUBFC, 2, Result).addReg(InVals[2]).addReg(InVals[0]);
- BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(InVals[3]).addReg(InVals[1]);
+ BuildMI(BB, PPC::SUBFC, 2, Result).addReg(Tmp3).addReg(Tmp1);
+ BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(Tmp4).addReg(Tmp2);
}
return Result+N.ResNo;
}
unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
unsigned SHReg = FoldIfWideZeroExtend(N.getOperand(2));
- Tmp1 = MakeReg(MVT::i32);
- Tmp2 = MakeReg(MVT::i32);
- Tmp3 = MakeReg(MVT::i32);
- unsigned Tmp4 = MakeReg(MVT::i32);
- unsigned Tmp5 = MakeReg(MVT::i32);
- unsigned Tmp6 = MakeReg(MVT::i32);
+ Tmp1 = MakeIntReg();
+ Tmp2 = MakeIntReg();
+ Tmp3 = MakeIntReg();
+ unsigned Tmp4 = MakeIntReg();
+ unsigned Tmp5 = MakeIntReg();
+ unsigned Tmp6 = MakeIntReg();
BuildMI(BB, PPC::SUBFIC, 2, Tmp1).addReg(SHReg).addSImm(32);
if (ISD::SHL_PARTS == opcode) {
BuildMI(BB, PPC::SLW, 2, Tmp2).addReg(ShiftOpHi).addReg(SHReg);
BuildMI(BB, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
// Select correct least significant half if the shift amount > 32
BB = TmpMBB;
- unsigned Tmp7 = MakeReg(MVT::i32);
+ unsigned Tmp7 = MakeIntReg();
BuildMI(BB, PPC::OR, 2, Tmp7).addReg(Tmp6).addReg(Tmp6);
TmpMBB->addSuccessor(PhiMBB);
BB = PhiMBB;
return Result+N.ResNo;
}
- case ISD::FP_TO_UINT:
case ISD::FP_TO_SINT: {
- bool U = (ISD::FP_TO_UINT == opcode);
Tmp1 = SelectExpr(N.getOperand(0));
- if (!U) {
- Tmp2 = MakeReg(MVT::f64);
- BuildMI(BB, PPC::FCTIWZ, 1, Tmp2).addReg(Tmp1);
- int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
- addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(Tmp2), FrameIdx);
- addFrameReference(BuildMI(BB, PPC::LWZ, 2, Result), FrameIdx, 4);
- return Result;
- } else {
- unsigned Zero = getConstDouble(0.0);
- unsigned MaxInt = getConstDouble((1LL << 32) - 1);
- unsigned Border = getConstDouble(1LL << 31);
- unsigned UseZero = MakeReg(MVT::f64);
- unsigned UseMaxInt = MakeReg(MVT::f64);
- unsigned UseChoice = MakeReg(MVT::f64);
- unsigned TmpReg = MakeReg(MVT::f64);
- unsigned TmpReg2 = MakeReg(MVT::f64);
- unsigned ConvReg = MakeReg(MVT::f64);
- unsigned IntTmp = MakeReg(MVT::i32);
- unsigned XorReg = MakeReg(MVT::i32);
- MachineFunction *F = BB->getParent();
- int FrameIdx = F->getFrameInfo()->CreateStackObject(8, 8);
- // Update machine-CFG edges
- MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
- MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
- MachineBasicBlock *OldMBB = BB;
- ilist<MachineBasicBlock>::iterator It = BB; ++It;
- F->getBasicBlockList().insert(It, XorMBB);
- F->getBasicBlockList().insert(It, PhiMBB);
- BB->addSuccessor(XorMBB);
- BB->addSuccessor(PhiMBB);
- // Convert from floating point to unsigned 32-bit value
- // Use 0 if incoming value is < 0.0
- BuildMI(BB, PPC::FSEL, 3, UseZero).addReg(Tmp1).addReg(Tmp1).addReg(Zero);
- // Use 2**32 - 1 if incoming value is >= 2**32
- BuildMI(BB, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(Tmp1);
- BuildMI(BB, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt).addReg(UseZero)
- .addReg(MaxInt);
- // Subtract 2**31
- BuildMI(BB, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
- // Use difference if >= 2**31
- BuildMI(BB, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice).addReg(Border);
- BuildMI(BB, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
- .addReg(UseChoice);
- // Convert to integer
- BuildMI(BB, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
- addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(ConvReg), FrameIdx);
- addFrameReference(BuildMI(BB, PPC::LWZ, 2, IntTmp), FrameIdx, 4);
- BuildMI(BB, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
- BuildMI(BB, PPC::B, 1).addMBB(XorMBB);
-
- // XorMBB:
- // add 2**31 if input was >= 2**31
- BB = XorMBB;
- BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
- XorMBB->addSuccessor(PhiMBB);
-
- // PhiMBB:
- // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
- BB = PhiMBB;
- BuildMI(BB, PPC::PHI, 4, Result).addReg(IntTmp).addMBB(OldMBB)
- .addReg(XorReg).addMBB(XorMBB);
- return Result;
- }
- assert(0 && "Should never get here");
- return 0;
+ Tmp2 = MakeFPReg();
+ BuildMI(BB, PPC::FCTIWZ, 1, Tmp2).addReg(Tmp1);
+ int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
+ addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(Tmp2), FrameIdx);
+ addFrameReference(BuildMI(BB, PPC::LWZ, 2, Result), FrameIdx, 4);
+ return Result;
}
case ISD::SETCC: {
switch (CC) {
default: Node->dump(); assert(0 && "Unhandled SetCC condition"); abort();
case ISD::SETEQ:
- Tmp2 = MakeReg(MVT::i32);
+ Tmp2 = MakeIntReg();
BuildMI(BB, PPC::CNTLZW, 1, Tmp2).addReg(Tmp1);
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp2).addImm(27)
.addImm(5).addImm(31);
break;
case ISD::SETNE:
- Tmp2 = MakeReg(MVT::i32);
+ Tmp2 = MakeIntReg();
BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(-1);
BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp2).addReg(Tmp1);
break;
.addImm(31).addImm(31);
break;
case ISD::SETGT:
- Tmp2 = MakeReg(MVT::i32);
- Tmp3 = MakeReg(MVT::i32);
+ Tmp2 = MakeIntReg();
+ Tmp3 = MakeIntReg();
BuildMI(BB, PPC::NEG, 2, Tmp2).addReg(Tmp1);
BuildMI(BB, PPC::ANDC, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
switch (CC) {
default: assert(0 && "Unhandled SetCC condition"); abort();
case ISD::SETEQ:
- Tmp2 = MakeReg(MVT::i32);
- Tmp3 = MakeReg(MVT::i32);
+ Tmp2 = MakeIntReg();
+ Tmp3 = MakeIntReg();
BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(1);
BuildMI(BB, PPC::LI, 1, Tmp3).addSImm(0);
BuildMI(BB, PPC::ADDZE, 1, Result).addReg(Tmp3);
break;
case ISD::SETNE:
- Tmp2 = MakeReg(MVT::i32);
- Tmp3 = MakeReg(MVT::i32);
+ Tmp2 = MakeIntReg();
+ Tmp3 = MakeIntReg();
BuildMI(BB, PPC::NOR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
BuildMI(BB, PPC::ADDIC, 2, Tmp3).addReg(Tmp2).addSImm(-1);
BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp3).addReg(Tmp2);
break;
case ISD::SETLT:
- Tmp2 = MakeReg(MVT::i32);
- Tmp3 = MakeReg(MVT::i32);
+ Tmp2 = MakeIntReg();
+ Tmp3 = MakeIntReg();
BuildMI(BB, PPC::ADDI, 2, Tmp2).addReg(Tmp1).addSImm(1);
BuildMI(BB, PPC::AND, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
.addImm(31).addImm(31);
break;
case ISD::SETGT:
- Tmp2 = MakeReg(MVT::i32);
+ Tmp2 = MakeIntReg();
BuildMI(BB, PPC::RLWINM, 4, Tmp2).addReg(Tmp1).addImm(1)
.addImm(31).addImm(31);
BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp2).addImm(1);
}
}
- bool Inv;
- unsigned CCReg = SelectCC(N, Opc, Inv, Tmp2);
- MoveCRtoGPR(CCReg, Inv, Tmp2, Result);
+ unsigned CCReg = SelectCC(N.getOperand(0), N.getOperand(1), CC);
+ MoveCRtoGPR(CCReg, CC, Result);
return Result;
}
- case ISD::SELECT: {
- SDNode *Cond = N.getOperand(0).Val;
- ISD::CondCode CC;
- if (Cond->getOpcode() == ISD::SETCC &&
- !MVT::isInteger(N.getOperand(1).getValueType()) &&
- !MVT::isInteger(Cond->getOperand(1).getValueType()) &&
- cast<CondCodeSDNode>(Cond->getOperand(2))->get() != ISD::SETEQ &&
- cast<CondCodeSDNode>(Cond->getOperand(2))->get() != ISD::SETNE) {
- MVT::ValueType VT = Cond->getOperand(0).getValueType();
- ISD::CondCode CC = cast<CondCodeSDNode>(Cond->getOperand(2))->get();
- unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
- unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
-
- ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Cond->getOperand(1));
+
+ case ISD::SELECT_CC: {
+ ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(4))->get();
+ if (!MVT::isInteger(N.getOperand(0).getValueType()) &&
+ !MVT::isInteger(N.getOperand(2).getValueType()) &&
+ CC != ISD::SETEQ && CC != ISD::SETNE) {
+ MVT::ValueType VT = N.getOperand(0).getValueType();
+ unsigned TV = SelectExpr(N.getOperand(2)); // Use if TRUE
+ unsigned FV = SelectExpr(N.getOperand(3)); // Use if FALSE
+
+ ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N.getOperand(1));
if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
switch(CC) {
default: assert(0 && "Invalid FSEL condition"); abort();
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETUGE:
case ISD::SETGE:
- Tmp1 = SelectExpr(Cond->getOperand(0)); // Val to compare against
+ Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
return Result;
case ISD::SETUGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETULE:
case ISD::SETLE: {
- if (Cond->getOperand(0).getOpcode() == ISD::FNEG) {
- Tmp2 = SelectExpr(Cond->getOperand(0).getOperand(0));
+ if (N.getOperand(0).getOpcode() == ISD::FNEG) {
+ Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
} else {
Tmp2 = MakeReg(VT);
- Tmp1 = SelectExpr(Cond->getOperand(0)); // Val to compare against
+ Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
}
BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
}
} else {
Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
- Tmp1 = SelectExpr(Cond->getOperand(0)); // Val to compare against
- Tmp2 = SelectExpr(Cond->getOperand(1));
+ Tmp1 = SelectExpr(N.getOperand(0)); // Val to compare against
+ Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = MakeReg(VT);
switch(CC) {
default: assert(0 && "Invalid FSEL condition"); abort();
assert(0 && "Should never get here");
}
- bool Inv;
- unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
- unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
- unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
-
+ // If the False value only has one use, we can generate better code by
+ // selecting it in the fallthrough basic block rather than here, which
+ // increases register pressure.
+ unsigned TrueValue = SelectExpr(N.getOperand(2));
+ unsigned FalseValue = SelectExpr(N.getOperand(3));
+ unsigned CCReg = SelectCC(N.getOperand(0), N.getOperand(1), CC);
+ Opc = getBCCForSetCC(CC);
+
// Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
case ISD::Constant:
switch (N.getValueType()) {
default: assert(0 && "Cannot use constants of this type!");
- case MVT::i1:
- BuildMI(BB, PPC::LI, 1, Result)
- .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
- break;
case MVT::i32:
{
int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
if (v < 32768 && v >= -32768) {
BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
} else {
- Tmp1 = MakeReg(MVT::i32);
+ Tmp1 = MakeIntReg();
BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
}
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
return Result;
-
- case ISD::UINT_TO_FP:
- case ISD::SINT_TO_FP: {
- assert (N.getOperand(0).getValueType() == MVT::i32
- && "int to float must operate on i32");
- bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
- Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
- Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
- Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
-
- int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
- MachineConstantPool *CP = BB->getParent()->getConstantPool();
-
- if (IsUnsigned) {
- unsigned ConstF = getConstDouble(0x1.000000p52);
- // Store the hi & low halves of the fp value, currently in int regs
- BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
- addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
- addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
- addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
- // Generate the return value with a subtract
- BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
- } else {
- unsigned ConstF = getConstDouble(0x1.000008p52);
- unsigned TmpL = MakeReg(MVT::i32);
- // Store the hi & low halves of the fp value, currently in int regs
- BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
- addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
- BuildMI(BB, PPC::XORIS, 2, TmpL).addReg(Tmp1).addImm(0x8000);
- addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
- addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
- // Generate the return value with a subtract
- BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
- }
- return Result;
- }
}
return 0;
}
BuildMI(BB, PPC::B, 1).addMBB(Dest);
return;
}
- case ISD::BRCOND:
- case ISD::BRCONDTWOWAY:
+ case ISD::BR_CC:
+ case ISD::BRTWOWAY_CC:
SelectBranchCC(N);
return;
case ISD::CopyToReg:
Select(N.getOperand(0));
- Tmp1 = SelectExpr(N.getOperand(1));
- Tmp2 = cast<RegSDNode>(N)->getReg();
+ Tmp1 = SelectExpr(N.getOperand(2));
+ Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (Tmp1 != Tmp2) {
- if (N.getOperand(1).getValueType() == MVT::f64 ||
- N.getOperand(1).getValueType() == MVT::f32)
+ if (N.getOperand(2).getValueType() == MVT::f64 ||
+ N.getOperand(2).getValueType() == MVT::f32)
BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
else
BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
return;
case ISD::ImplicitDef:
Select(N.getOperand(0));
- BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
+ BuildMI(BB, PPC::IMPLICIT_DEF, 0,
+ cast<RegisterSDNode>(N.getOperand(1))->getReg());
return;
case ISD::RET:
switch (N.getNumOperands()) {
projects / oota-llvm.git / blobdiff