Add all of the data stream intrinsics and instructions. woo

[oota-llvm.git] / lib / Target / PowerPC / PPCInstrFormats.td

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 9f87b278e674d18039344b69f766db667c501b2b..10ac79b1c2e34eb698ccb75cf07a904b40514f2e 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -325,6 +325,26 @@ class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
   : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
 }
 
+// DSS_Form - Form X instruction, used for altivec dss* instructions.
+class DSS_Form<bits<10> xo, dag OL, string asmstr, 
+                      InstrItinClass itin, list<dag> pattern>
+  : I<31, OL, asmstr, itin> {
+  bits<1> T;
+  bits<2> STRM;
+  bits<5> A;
+  bits<5> B;
+
+  let Pattern = pattern;
+
+  let Inst{6}     = T;
+  let Inst{7-8}   = 0;
+  let Inst{9-10}  = STRM;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
 // 1.7.7 XL-Form
 class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
                InstrItinClass itin>
@@ -589,7 +609,11 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
   let Inst{31}    = RC;
 }
 
+
+
 // E-1 VA-Form
+
+// VAForm_1 - DACB ordering.
 class VAForm_1<bits<6> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OL, asmstr, itin> {
@@ -607,6 +631,24 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr,
   let Inst{26-31} = xo;
 }
 
+// VAForm_1a - DABC ordering.
+class VAForm_1a<bits<6> xo, dag OL, string asmstr,
+                InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VA;
+  bits<5> VB;
+  bits<5> VC;
+
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = VA;
+  let Inst{16-20} = VB;
+  let Inst{21-25} = VC;
+  let Inst{26-31} = xo;
+}
+
 class VAForm_2<bits<6> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OL, asmstr, itin> {
@@ -677,6 +719,33 @@ class VXForm_3<bits<11> xo, dag OL, string asmstr,
   let Inst{21-31} = xo;
 }
 
+/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
+class VXForm_4<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
+class VXForm_5<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VB;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = 0;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
 
 // E-4 VXR-Form
 class VXRForm_1<bits<10> xo, dag OL, string asmstr,