// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//
field bits<32> Inst;
bit PPC64 = 0; // Default value, override with isPPC64
- bit VMX = 0; // Default value, override with isVMX
let Name = "";
let Namespace = "PPC";
let OperandList = OL;
let AsmString = asmstr;
let Itinerary = itin;
+
+ /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
+ /// these must be reflected there! See comments there for what these are.
+ bits<1> PPC970_First = 0;
+ bits<1> PPC970_Single = 0;
+ bits<1> PPC970_Cracked = 0;
+ bits<3> PPC970_Unit = 0;
}
+class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
+class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
+class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
+class PPC970_MicroCode;
+
+class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
+class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
+class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
+class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
+class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
+class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
+class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
+class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
+
+
// 1.7.1 I-Form
class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
}
+// DCB_Form - Form X instruction, used for dcb* instructions.
+class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<31, OL, asmstr, itin> {
+ bits<5> A;
+ bits<5> B;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = immfield;
+ let Inst{11-15} = A;
+ let Inst{16-20} = B;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+
+// DSS_Form - Form X instruction, used for altivec dss* instructions.
+class DSS_Form<bits<10> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<31, OL, asmstr, itin> {
+ bits<1> T;
+ bits<2> STRM;
+ bits<5> A;
+ bits<5> B;
+
+ let Pattern = pattern;
+
+ let Inst{6} = T;
+ let Inst{7-8} = 0;
+ let Inst{9-10} = STRM;
+ let Inst{11-15} = A;
+ let Inst{16-20} = B;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
// 1.7.7 XL-Form
class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin>
}
class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr,
- InstrItinClass itin>
+ InstrItinClass itin, list<dag> pattern>
: I<opcode, OL, asmstr, itin> {
bits<5> BO;
bits<5> BI;
bits<2> BH;
+ let Pattern = pattern;
+
let Inst{6-10} = BO;
let Inst{11-15} = BI;
let Inst{16-18} = 0;
}
class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
- dag OL, string asmstr, InstrItinClass itin>
- : XLForm_2<opcode, xo, lk, OL, asmstr, itin> {
+ dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
+ : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> {
let BO = bo;
let BI = bi;
let BH = 0;
let Inst{31} = RC;
}
+
+
// E-1 VA-Form
+
+// VAForm_1 - DACB ordering.
class VAForm_1<bits<6> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<4, OL, asmstr, itin> {
bits<5> VD;
bits<5> VA;
+ bits<5> VC;
+ bits<5> VB;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = VA;
+ let Inst{16-20} = VB;
+ let Inst{21-25} = VC;
+ let Inst{26-31} = xo;
+}
+
+// VAForm_1a - DABC ordering.
+class VAForm_1a<bits<6> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> VA;
bits<5> VB;
bits<5> VC;
let Inst{26-31} = xo;
}
+class VAForm_2<bits<6> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> VA;
+ bits<5> VB;
+ bits<4> SH;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = VA;
+ let Inst{16-20} = VB;
+ let Inst{21} = 0;
+ let Inst{22-25} = SH;
+ let Inst{26-31} = xo;
+}
+
// E-2 VX-Form
class VXForm_1<bits<11> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
let Inst{21-31} = xo;
}
+class VXForm_3<bits<11> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> IMM;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = IMM;
+ let Inst{16-20} = 0;
+ let Inst{21-31} = xo;
+}
+
+/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
+class VXForm_4<bits<11> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VD;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = 0;
+ let Inst{16-20} = 0;
+ let Inst{21-31} = xo;
+}
+
+/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
+class VXForm_5<bits<11> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VB;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = 0;
+ let Inst{11-15} = 0;
+ let Inst{16-20} = VB;
+ let Inst{21-31} = xo;
+}
+
// E-4 VXR-Form
-class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
+class VXRForm_1<bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<4, OL, asmstr, itin> {
bits<5> VD;
bits<5> VA;
bits<5> VB;
+ bit RC = 0;
let Pattern = pattern;
let Inst{6-10} = VD;
let Inst{11-15} = VA;
let Inst{16-20} = VB;
- let Inst{21} = rc;
+ let Inst{21} = RC;
let Inst{22-31} = xo;
}
//===----------------------------------------------------------------------===//
-def NoItin : InstrItinClass;
class Pseudo<dag OL, string asmstr, list<dag> pattern>
- : I<0, OL, asmstr, NoItin> {
+ : I<0, OL, asmstr, NoItinerary> {
let PPC64 = 0;
let VMX = 0;
let Pattern = pattern;
projects / oota-llvm.git / blobdiff